홈 로직 및 전압 변환 구성 가능 및 프로그래머블 로직 IC 멀티바이브레이터 원샷
홈
로직 및 전압 변환
구성 가능 및 프로그래머블 로직 IC
멀티바이브레이터 원샷

SN74LVC1G123

활성

슈미트 트리거 입력을 지원하는 단일 재트리거 가능 단안정 멀티바이브레이터

지금 주문
데이터 시트

SN74LVC1G123

활성
데이터 시트 지금 주문

제품 상세 정보

Number of channels 1 Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Technology family LVC Input type Schmitt-Trigger Output type Push-Pull Supply current (µA) 20 IOL (max) (mA) 32 IOH (max) (mA) -32 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 125 Rating Catalog
Number of channels 1 Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Technology family LVC Input type Schmitt-Trigger Output type Push-Pull Supply current (µA) 20 IOL (max) (mA) 32 IOH (max) (mA) -32 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 125 Rating Catalog
DSBGA (YZP) 8 2.8125 mm² 2.25 x 1.25 SSOP (DCT) 8 11.8 mm² 2.95 x 4 VSSOP (DCU) 8 6.2 mm² 2 x 3.1
  • Available in the Texas Instruments NanoFree™ Package
  • Supports 5V VCC Operation
  • Inputs Accept Voltages to 5.5V
  • Max tpd of 8ns at 3.3V
  • Supports Mixed-Mode Voltage Operation on All Ports
  • Supports Down Translation to VCC
  • Schmitt-Trigger Circuitry on A and B Inputs for Slow Input Transition Rates
  • Edge Triggered From Active-High or Active-Low Gated Logic Inputs
  • Retriggerable for Very Long Output Pulses, Up to 100% Duty Cycle
  • Overriding Clear Terminates Output Pulse
  • Glitch-Free Power-Up Reset on Outputs
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000V Human-Body Model (A114-A)
    • 200V Machine Model (A115-A)
    • 1000V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoFree™ Package
  • Supports 5V VCC Operation
  • Inputs Accept Voltages to 5.5V
  • Max tpd of 8ns at 3.3V
  • Supports Mixed-Mode Voltage Operation on All Ports
  • Supports Down Translation to VCC
  • Schmitt-Trigger Circuitry on A and B Inputs for Slow Input Transition Rates
  • Edge Triggered From Active-High or Active-Low Gated Logic Inputs
  • Retriggerable for Very Long Output Pulses, Up to 100% Duty Cycle
  • Overriding Clear Terminates Output Pulse
  • Glitch-Free Power-Up Reset on Outputs
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000V Human-Body Model (A114-A)
    • 200V Machine Model (A115-A)
    • 1000V Charged-Device Model (C101)

The SN74LVC1G123 device is a single retriggerable monostable multivibrator designed for 1.65V to 5.5V VCC operation.

This monostable multivibrator features output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear ( CLR) input goes high.

The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A and B inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.

The SN74LVC1G123 device is a single retriggerable monostable multivibrator designed for 1.65V to 5.5V VCC operation.

This monostable multivibrator features output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear ( CLR) input goes high.

The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A and B inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.
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기술 자료

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30개 모두 보기
유형 직함 날짜
* Data sheet SN74LVC1G123 Single Retriggerable Monostable Multivibrator With Schmitt-Trigger Inputs datasheet (Rev. E) PDF | HTML 2024/03/01
Product overview Configurable Timed Reset Using Discrete Logic (Rev. A) PDF | HTML 2023/05/02
Application note The Davies Sinusoidal Generator PDF | HTML 2022/10/31
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Application note Designing With the SN74LVC1G123 Monostable Multivibrator (Rev. A) PDF | HTML 2020/03/13
Selection guide Little Logic Guide 2018 (Rev. G) 2018/07/06
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note How to Select Little Logic (Rev. A) 2016/07/26
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004/11/04
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 2003/11/06
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 2002/12/18
Application note Texas Instruments Little Logic Application Report 2002/11/01
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002/06/13
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002/05/10
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 2002/03/27
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997/12/01
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note LVC Characterization Information 1996/12/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Design guide Low-Voltage Logic (LVC) Designer's Guide 1996/09/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01

설계 및 개발

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평가 보드

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사용 설명서: PDF
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시뮬레이션 모델

HSPICE Model for SN74LVC1G123

SCEJ262.ZIP (98 KB) - HSpice Model
다운로드
시뮬레이션 모델

SN74LVC1G123 IBIS Model

SCEM427.ZIP (45 KB) - IBIS Model
다운로드
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패키지 핀 CAD 기호, 풋프린트 및 3D 모델
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SSOP (DCT) 8 Ultra Librarian
VSSOP (DCU) 8 Ultra Librarian
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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