SN74LVC2G02

활성

2채널, 2입력, 1.65V~5.5V NOR 게이트

제품 상세 정보

Technology family LVC Number of channels 2 Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Output type Push-Pull Input type Standard CMOS Features Over-voltage tolerant Inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Number of channels 2 Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Output type Push-Pull Input type Standard CMOS Features Over-voltage tolerant Inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
DSBGA (YZP) 8 2.8125 mm² 2.25 x 1.25 SSOP (DCT) 8 11.8 mm² 2.95 x 4 VSSOP (DCU) 8 6.2 mm² 2 x 3.1
  • Available in the Texas Instruments
    NanoFree™ package
  • Supports 5-V VCC operation
  • Inputs accept voltages to 5.5 V
  • Max tpd of 4.9 ns at 3.3 V
  • Low power consumption, 10-µA Max ICC
  • ±24-mA Output drive at 3.3 V
  • Typical VOLP (output ground bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (output VOH undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100 mA er JESD 78, class II
  • ESD protection exceeds JESD 22
    • 2000-V Human-body model (A114-A)
    • 1000-V Charged-device model (C101)
  • Available in the Texas Instruments
    NanoFree™ package
  • Supports 5-V VCC operation
  • Inputs accept voltages to 5.5 V
  • Max tpd of 4.9 ns at 3.3 V
  • Low power consumption, 10-µA Max ICC
  • ±24-mA Output drive at 3.3 V
  • Typical VOLP (output ground bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (output VOH undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100 mA er JESD 78, class II
  • ESD protection exceeds JESD 22
    • 2000-V Human-body model (A114-A)
    • 1000-V Charged-device model (C101)

This dual 2-input positive-NOR gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G02 device performs the Boolean function Y = A + B or Y = A × B in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This dual 2-input positive-NOR gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G02 device performs the Boolean function Y = A + B or Y = A × B in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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관심 가지실만한 유사 제품

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비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
SN74AUP2G02 활성 2채널, 2입력, 0.8V~3.6V 저전력 NOR 게이트 Smaller voltage range (0.8V to 3.6V), longer average propagation delay (8ns), lower average drive strength (4mA)

기술 자료

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27개 모두 보기
유형 직함 날짜
* Data sheet Dual 2-Input Positive-NOR Gate, SN74LVC2G02 datasheet (Rev. N) 2014/02/19
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Little Logic Guide 2018 (Rev. G) 2018/07/06
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note How to Select Little Logic (Rev. A) 2016/07/26
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004/11/04
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 2003/11/06
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 2002/12/18
Application note Texas Instruments Little Logic Application Report 2002/11/01
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002/06/13
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002/05/10
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 2002/03/27
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997/12/01
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note LVC Characterization Information 1996/12/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Design guide Low-Voltage Logic (LVC) Designer's Guide 1996/09/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01

설계 및 개발

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평가 보드

5-8-LOGIC-EVM — 5핀~8핀 DCK, DCT, DCU, DRL 및 DBV 패키지용 일반 논리 평가 모듈

5~8핀 수의 DCK, DCT, DCU, DRL 또는 DBV 패키지가 있는 모든 디바이스를 지원하도록 설계된 유연한 EVM.
사용 설명서: PDF
TI.com에서 구매 불가
시뮬레이션 모델

SN74LVC2G02 Behavioral SPICE Model

SCEM624.ZIP (7 KB) - PSpice Model
시뮬레이션 모델

SN74LVC2G02 IBIS Model (Rev. A)

SCEM287A.ZIP (52 KB) - IBIS Model
패키지 CAD 기호, 풋프린트 및 3D 모델
DSBGA (YZP) 8 Ultra Librarian
SSOP (DCT) 8 Ultra Librarian
VSSOP (DCU) 8 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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