SN74LVCH16373A

Name: SN74LVCH16373A
Brand: TI
SKU: SN74LVCH16373A
Price: 0.413 USD

활성

3상 출력을 지원하는 16bit 투명 D형 래치

지금 주문

데이터 시트

document-pdfAcrobat SN74LVCH16373A 16-Bit Transparent D-Type Latch With 3-State Outputs datasheet (Rev. N) (영어) PDF | HTML

SN74LVCH16373A

활성

데이터 시트

지금 주문

제품 상세 정보

Number of channels

Technology family

LVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

3.6

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

100

IOL (max) (mA)

IOH (max) (mA)

-24

Supply current (max) (µA)

Features

Balanced outputs, Flow-through pinout, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Number of channels

Technology family

LVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

3.6

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

100

IOL (max) (mA)

IOH (max) (mA)

-24

Supply current (max) (µA)

Features

Balanced outputs, Flow-through pinout, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 125

Rating

Catalog

SSOP (DL)

164.358 mm² 15.88 x 10.35

TSSOP (DGG)

101.25 mm² 12.5 x 8.1

TVSOP (DGV)

62.08 mm² 9.7 x 6.4

Member of the Texas Instruments Widebus Family
Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
> 2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Bus Hold on Data Inputs Eliminates the Need for External Pull-up or Pull-down Resistors
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

Member of the Texas Instruments Widebus Family
Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
> 2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Bus Hold on Data Inputs Eliminates the Need for External Pull-up or Pull-down Resistors
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

This 16-bit transparent D-type latch is designed for 1.65-V to 3.6-V V_CC operation.

filter

기타 D형 래치 찾기

다운로드 스크립트와 함께 비디오 보기 동영상

관심 가지실만한 유사 제품

open-in-new

대안 비교

비교 대상 장치보다 업그레이드된 기능을 지원하는 드롭인 대체품

SN74AUC16373

활성

3상 출력을 지원하는 16bit 투명 D형 래치 Smaller voltage range (0.8V to 2.7V), shorter average propagation delay (1.7ns)

비교 대상 장치와 유사한 기능

SN74LVC373A

활성

3상 출력을 지원하는 8진 투명 D형 래치 Voltage range 1.65V to 3.6V, average propagation delay 5.5ns, average drive strength 24mA

기술 자료

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29개 모두 보기

	유형	직함		날짜
*	Data sheet	SN74LVCH16373A 16-Bit Transparent D-Type Latch With 3-State Outputs datasheet (Rev. N)	PDF \| HTML	2014/07/24
	Application note	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	2022/12/15
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		2021/07/26
	Application note	An Overview of Bus-Hold Circuit and the Applications (Rev. B)		2018/09/17
	Selection guide	Little Logic Guide 2018 (Rev. G)		2018/07/06
	Selection guide	Logic Guide (Rev. AB)		2017/06/12
	Application note	How to Select Little Logic (Rev. A)		2016/07/26
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		2015/12/02
	User guide	LOGIC Pocket Data Book (Rev. B)		2007/01/16
	Product overview	Design Summary for WCSP Little Logic (Rev. B)		2004/11/04
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		2004/07/08
	Application note	Selecting the Right Level Translation Solution (Rev. A)		2004/06/22
	User guide	Signal Switch Data Book (Rev. A)		2003/11/14
	Application note	Use of the CMOS Unbuffered Inverter in Oscillator Circuits		2003/11/06
	User guide	LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)		2002/12/18
	Application note	Texas Instruments Little Logic Application Report		2002/11/01
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		2002/08/29
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards		2002/06/13
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)		2002/05/22
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices		2002/05/10
	More literature	STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS		2002/03/27
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices		1997/12/01
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)		1997/08/01
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)		1997/06/01
	Application note	LVC Characterization Information		1996/12/01
	Application note	Input and Output Characteristics of Digital Integrated Circuits		1996/10/01
	Application note	Live Insertion		1996/10/01
	Design guide	Low-Voltage Logic (LVC) Designer's Guide		1996/09/01
	Application note	Understanding Advanced Bus-Interface Products Design Guide		1996/05/01