홈
로직 및 전압 변환
플립플롭, 래치 및 레지스터
D형 래치
홈
로직 및 전압 변환
플립플롭, 래치 및 레지스터
D형 래치

SN74LVTH16373-EP

활성

3상 출력을 지원하는 향상된 제품 3.3V ABT 16비트 트랜스페어런스 D형 래치

alarm알림 지금 주문
데이터 시트

SN74LVTH16373-EP

활성
데이터 시트 지금 주문

제품 상세 정보

Number of channels 16 Technology family LVT Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 160 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 5000 Features Bus-hold, Flow-through pinout, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Operating temperature range (°C) -40 to 85 Rating HiRel Enhanced Product
Number of channels 16 Technology family LVT Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 160 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 5000 Features Bus-hold, Flow-through pinout, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Operating temperature range (°C) -40 to 85 Rating HiRel Enhanced Product
SSOP (DL) 48 164.358 mm² 15.88 x 10.35 TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources
    (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Member of the Texas Instruments Widebus™ Family
  • State-of-the-Art Advanced BiCMOS Technology
    (ABT) Design for 3.3-V Operation and Low Static-
    Power Dissipation
  • Supports Mixed-Mode Signal Operation (5-V Input
    and Output Voltages With 3.3-V VCC)
  • Supports Unregulated Battery Operation Down to
    2.7 V
  • Typical VOLP (Output Ground Bounce) < 0.8 V
    at VCC = 3.3 V, TA = 25°C
  • Ioff and Power-Up Tri-State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for
    External Pullup/Pulldown Resistors
  • Distributed VCC and GND Pins Minimize High-
    Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 500 mA Per
    JESD 17
  • ESD Protection Exceeds JESD 22
    • 4000-V Human Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources
    (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Member of the Texas Instruments Widebus™ Family
  • State-of-the-Art Advanced BiCMOS Technology
    (ABT) Design for 3.3-V Operation and Low Static-
    Power Dissipation
  • Supports Mixed-Mode Signal Operation (5-V Input
    and Output Voltages With 3.3-V VCC)
  • Supports Unregulated Battery Operation Down to
    2.7 V
  • Typical VOLP (Output Ground Bounce) < 0.8 V
    at VCC = 3.3 V, TA = 25°C
  • Ioff and Power-Up Tri-State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for
    External Pullup/Pulldown Resistors
  • Distributed VCC and GND Pins Minimize High-
    Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 500 mA Per
    JESD 17
  • ESD Protection Exceeds JESD 22
    • 4000-V Human Body Model (A114-A)
    • 200-V Machine Model (A115-A)

The SN74LVTH16373 is a 16-bit transparent D-type latch with tri-state outputs designed for low-voltage (3.3 V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

The SN74LVTH16373 is a 16-bit transparent D-type latch with tri-state outputs designed for low-voltage (3.3 V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
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기술 자료

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18개 모두 보기
유형 직함 날짜
* Data sheet SN74LVTH16373-EP 3.3-V ABT 16-Bit Transparent D-Type Latch With Tri-State Outputs datasheet (Rev. B) PDF | HTML 2016/06/29
* VID SN74LVTH16373-EP VID V6204712 2016/06/21
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022/12/15
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002/05/10
Selection guide Advanced Bus Interface Logic Selection Guide 2001/01/09
Application note LVT-to-LVTH Conversion 1998/12/08
Application note LVT Family Characteristics (Rev. A) 1998/03/01
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

시뮬레이션 모델

SN74LVTH16373 IBIS Model (Rev. C)

SCEM076C.ZIP (32 KB) - IBIS Model
다운로드
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
SSOP (DL) 48 Ultra Librarian
TSSOP (DGG) 48 Ultra Librarian
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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