THS0842
- Dual Simultaneous Sample and Hold Inputs
- Differential or Single-Ended Analog Inputs
- 8-Bit Resolution 40 MSPS Sampling Analog-to-Digital Converter (ADC)
- Single or Dual Parallel Bus Output
- Low Power Consumption: 275 mW Typ Using External References
- Wide Analog Input Bandwidth: 600 MHz Typ
- 3.3 V Single-Supply Operation
- 3.3 V TTL/CMOS-Compatible Digital I/O
- Internal or External Bottom and Top Reference Voltages
- Adjustable Reference Input Range
- Power-Down (Standby) Mode
- 48-Pin Thin Quad Flat Pack (TQFP) Package
- Applications
- Digital Communications (Baseband Sampling)
- Cable Modems
- Set Top Boxes
- Test Instruments
The THS0842 is a dual 8-bit 40 MSPS high-speed A/D converter. It alternately converts each analog input signal into 8-bit binary-coded digital words up to a maximum sampling rate of 40 MSPS with an 80 MHz clock. All digital inputs and outputs are 3.3 V TTL/CMOS-compatible.
Thanks to an innovative single-pipeline architecture implemented in a CMOS process and the 3.3 V supply, the device consumes very little power. In order to provide maximum flexibility, both bottom and top voltage references can be set from user supplied voltages. Alternately, if no external references are available, on-chip references can be used which are also made available externally. The full-scale range is 1 Vpp, depending on the analog supply voltage. If external references are available, the internal references can be powered down independently from the rest of the chip, resulting in an even greater power saving.
The device is specifically suited for the baseband sampling of wireless local loop (WLL) communication, cable modems, set top boxes (STBs), and test instruments.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | Dual-Input, 8-Bit, 40 MSPS, Low-Power ADC w/ Single or Dual Parallel Bus Output datasheet (Rev. A) | 2000/08/10 | |
| White paper | Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) | PDF | HTML | 2024/04/30 | |
| Application note | CDCE62005 as Clock Solution for High-Speed ADCs | 2008/09/04 | ||
| Application note | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008/06/08 | ||
| Application note | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008/06/02 | ||
| Application note | Noise Analysis for High Speed Op Amps (Rev. A) | 2005/01/17 | ||
| EVM User's guide | THS0842 EVM User's Guide (Rev. C) | 2000/09/28 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®
TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| TQFP (PFB) | 48 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치