제품 상세 정보

DSP type 1 C55x DSP (max) (MHz) 108, 144, 200 CPU 16-bit Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (°C) -40 to 85
DSP type 1 C55x DSP (max) (MHz) 108, 144, 200 CPU 16-bit Operating system DSP/BIOS, VLX Rating Catalog Operating temperature range (°C) -40 to 85
LQFP (PGE) 144 484 mm² 22 x 22 NFBGA (ZAY) 179 144 mm² 12 x 12
  • High-Performance, Low-Power, Fixed-Point TMS320C55™ Digital Signal Processor
    • 9.26-, 6.95-, 5-ns Instruction Cycle Time
    • 108-, 144-, 200-MHz Clock Rate
    • One/Two Instruction(s) Executed per Cycle
    • Dual Multipliers [Up to 400 Million Multiply-Accumulates per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
  • 32K × 16-Bit On-Chip RAM, Composed of:
    • 64K Bytes of Dual-Access RAM (DARAM) 8 Blocks of 4K × 16-Bit
  • 64K Bytes of One-Wait-State On-Chip ROM (32K × 16-Bit)
  • 8M × 16-Bit Maximum Addressable External Memory Space (Synchronous DRAM)
  • 16-Bit External Parallel Bus Memory Supporting Either:
    • External Memory Interface (EMIF) With GPIO Capabilities and Glueless Interface to:
      • Asynchronous Static RAM (SRAM)
      • Asynchronous EPROM
      • Synchronous DRAM (SDRAM)
    • 16-Bit Parallel Enhanced Host-Port Interface (EHPI) With GPIO Capabilities
  • Programmable Low-Power Control of Six Device Functional Domains
  • On-Chip Scan-Based Emulation Logic
  • On-Chip Peripherals
    • Two 20-Bit Timers
    • Watchdog Timer
    • Six-Channel Direct Memory Access (DMA) Controller
    • Three Multichannel Buffered Serial Ports (McBSPs)
    • Programmable Phase-Locked Loop Clock Generator
    • Seven (LQFP) or Eight (BGA) General-Purpose I/O (GPIO) Pins and a General- Purpose Output Pin (XF)
    • Inter-Integrated Circuit (I2C) Multi-Master and Slave Interface
    • Real-Time Clock (RTC) With Crystal Input, Separate Clock Domain, Separate Power Supply
  • IEEE Std 1149.1(1) (JTAG) Boundary Scan Logic
  • Packages:
    • 144-Terminal Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
    • 179-Terminal MicroStar BGA™ (Ball Grid Array) (GHH and ZHH Suffixes)
    • 1.2-V Core (108 MHz), 2.7-V - 3.6-V I/Os
  • 1.35-V Core (144 MHz), 2.7-V - 3.6-V I/Os
  • 1.6-V Core (200 MHz), 2.7-V - 3.6-V I/Os

C55x, eXpressDSP, Code Composer Studio, DSP/BIOS, RTDX, and XDS510 are trademarks of Texas Instruments.
TMS320C55x and MicroStar BGA are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
(1)IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

  • High-Performance, Low-Power, Fixed-Point TMS320C55™ Digital Signal Processor
    • 9.26-, 6.95-, 5-ns Instruction Cycle Time
    • 108-, 144-, 200-MHz Clock Rate
    • One/Two Instruction(s) Executed per Cycle
    • Dual Multipliers [Up to 400 Million Multiply-Accumulates per Second (MMACS)]
    • Two Arithmetic/Logic Units (ALUs)
    • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
  • 32K × 16-Bit On-Chip RAM, Composed of:
    • 64K Bytes of Dual-Access RAM (DARAM) 8 Blocks of 4K × 16-Bit
  • 64K Bytes of One-Wait-State On-Chip ROM (32K × 16-Bit)
  • 8M × 16-Bit Maximum Addressable External Memory Space (Synchronous DRAM)
  • 16-Bit External Parallel Bus Memory Supporting Either:
    • External Memory Interface (EMIF) With GPIO Capabilities and Glueless Interface to:
      • Asynchronous Static RAM (SRAM)
      • Asynchronous EPROM
      • Synchronous DRAM (SDRAM)
    • 16-Bit Parallel Enhanced Host-Port Interface (EHPI) With GPIO Capabilities
  • Programmable Low-Power Control of Six Device Functional Domains
  • On-Chip Scan-Based Emulation Logic
  • On-Chip Peripherals
    • Two 20-Bit Timers
    • Watchdog Timer
    • Six-Channel Direct Memory Access (DMA) Controller
    • Three Multichannel Buffered Serial Ports (McBSPs)
    • Programmable Phase-Locked Loop Clock Generator
    • Seven (LQFP) or Eight (BGA) General-Purpose I/O (GPIO) Pins and a General- Purpose Output Pin (XF)
    • Inter-Integrated Circuit (I2C) Multi-Master and Slave Interface
    • Real-Time Clock (RTC) With Crystal Input, Separate Clock Domain, Separate Power Supply
  • IEEE Std 1149.1(1) (JTAG) Boundary Scan Logic
  • Packages:
    • 144-Terminal Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
    • 179-Terminal MicroStar BGA™ (Ball Grid Array) (GHH and ZHH Suffixes)
    • 1.2-V Core (108 MHz), 2.7-V - 3.6-V I/Os
  • 1.35-V Core (144 MHz), 2.7-V - 3.6-V I/Os
  • 1.6-V Core (200 MHz), 2.7-V - 3.6-V I/Os

C55x, eXpressDSP, Code Composer Studio, DSP/BIOS, RTDX, and XDS510 are trademarks of Texas Instruments.
TMS320C55x and MicroStar BGA are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
(1)IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

The TMS320VC5503 fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The 64K bytes of on-chip memory on TMS320VC5503 is sufficient for many hand-held appliances, portable GPS systems, wireless speaker phones, portable PDAs, and gaming devices. Many of these appliances typically require 64K bytes or smaller amount of on-chip memory and need to operate in standby mode for more than 60% to 70% of the time. For applications that require more than 64K bytes of on-chip memory but less than 128K bytes of memory, Texas Instruments (TI) offers the TMS320VC5507 device, which is based on the TMS320C55x DSP core.

The general-purpose input and output functions and the 10-bit A/D provide sufficient pins for status, interrupts, and bit I/O for LCDs, keyboards, and media interfaces. The parallel interface operates in two modes, either as a slave to a microcontroller using the HPI port or as a parallel media interface using the asynchronous EMIF. Serial media is supported through three McBSPs.

The 5503 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM. Additional peripherals include real-time clock, watchdog timer, and I2C multi-master and slave interface. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The enhanced host-port interface (HPI) is a 16-bit parallel interface used to provide host processor access to 32K bytes of internal memory on the 5503. The HPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers, up to eight dedicated general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also included.

The 5503 is supported by the industry's award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments' algorithm standard, and the industry's largest third-party network. The Code Composer Studio IDE features code generation tools including a C Compiler and Visual Linker, simulator, RTDX™, XDS510™ emulation device drivers, and evaluation modules. The 5503 is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters,

The TMS320VC5503 fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

The 64K bytes of on-chip memory on TMS320VC5503 is sufficient for many hand-held appliances, portable GPS systems, wireless speaker phones, portable PDAs, and gaming devices. Many of these appliances typically require 64K bytes or smaller amount of on-chip memory and need to operate in standby mode for more than 60% to 70% of the time. For applications that require more than 64K bytes of on-chip memory but less than 128K bytes of memory, Texas Instruments (TI) offers the TMS320VC5507 device, which is based on the TMS320C55x DSP core.

The general-purpose input and output functions and the 10-bit A/D provide sufficient pins for status, interrupts, and bit I/O for LCDs, keyboards, and media interfaces. The parallel interface operates in two modes, either as a slave to a microcontroller using the HPI port or as a parallel media interface using the asynchronous EMIF. Serial media is supported through three McBSPs.

The 5503 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM. Additional peripherals include real-time clock, watchdog timer, and I2C multi-master and slave interface. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The enhanced host-port interface (HPI) is a 16-bit parallel interface used to provide host processor access to 32K bytes of internal memory on the 5503. The HPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers, up to eight dedicated general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also included.

The 5503 is supported by the industry's award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments' algorithm standard, and the industry's largest third-party network. The Code Composer Studio IDE features code generation tools including a C Compiler and Visual Linker, simulator, RTDX™, XDS510™ emulation device drivers, and evaluation modules. The 5503 is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters,

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TI에서 제공하는 설계 지원 없음

이 제품은 새로운 콘텐츠 또는 소프트웨어 업데이트와 같은 새로운 프로젝트에 대한 TI의 지속적인 설계 지원을 받지 않습니다. 가능한 경우 제품 폴더에서 관련 자료, 소프트웨어 및 툴을 확인할 수 있습니다. TI E2ETM 지원 포럼에서 보관된 정보를 검색할 수도 있습니다.

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
19개 모두 보기
유형 직함 날짜
* Data sheet TMS320VC5503 Fixed-Point Digital Signal Processor datasheet (Rev. J) 2008/01/22
* Errata TMS320VC5503 Digital Signal Processor Silicon Errata (Rev. C) 2008/04/14
* Errata TMS320VC5503/VC5506/VC5507/VC5509A Microstar BGA Discontinued and Redesigned 2022/05/10
User guide TMS320C55x DSP Peripherals Overview Reference Guide (Rev. K) 2011/12/15
User guide TMS320VC5503/5507/5509 DSP Host Port Interface (HPI) Reference Guide (Rev. C) 2009/06/11
Application note Board and System Design Considerations for the TMS320VC5503/06/07/09A DSPs 2008/11/19
Application note TMS320VC5503/VC5506/VC5507/C5509A Power Consumption Summary (Rev. C) 2008/09/05
Application note Using the TMS320VC5503/C5506/C5507/C5509/C5509A Bootloader (Rev. F) 2008/09/05
User guide TMS320VC5503/5507/5509/5510 Direct Memory Access(DMA) Controller Reference Guide (Rev. E) 2007/01/09
User guide TMS320VC5503/5507/5509/5510 DSP Timers Reference Guide (Rev. C) 2006/04/11
User guide TMS320VC5501/5502/5503/5507/5509 DSP Inter-Integrated Circuit (I2C) Module RG (Rev. D) 2005/10/17
User guide TMS320VC5501/5502/5503/5507/5509/5510 DSP (McBSP) Reference Guide (Rev. E) 2005/04/14
Application note Recommended Power Solutions For TMS320C5509A/07/03 2005/03/28
User guide TMS320C55x DSP CPU Programmer's Reference Supplement (Rev. G) 2005/02/24
Application note TMS320VC5503 Hardware Designer's Resource Guide 2004/06/25
User guide TMS320VC5503/5507/5509 DSP Real-Time Clock (RTC) Reference Guide (Rev. B) 2004/06/25
User guide TMS320VC5503/5507/5509 DSP External Memory Interface (EMIF) Reference Guide (Rev. A) 2004/06/04
User guide TMS320C55x DSP CPU Reference Guide (Rev. F) 2004/02/25
User guide TMS320C55x DSP Mnemonic Instruction Set Reference Guide (Rev. G) 2002/10/11

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

디버그 프로브

TMDSEMU200-U — XDS200 USB 디버그 프로브

XDS200은 TI 임베디드 디바이스 디버깅에 사용되는 디버그 프로브(에뮬레이터)입니다. XDS200은 저렴한 XDS110 및 고성능 XDS560v2에 비해 저렴한 비용으로 우수한 성능을 균형 있게 제공합니다. 단일 포드에서 광범위한 표준(IEEE1149.1, IEEE1149.7, SWD)을 지원합니다. 모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 Arm® 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 코어 추적의 경우 XDS560v2 PRO TRACE가 (...)

TI.com에서 구매 불가
디버그 프로브

TMDSEMU560V2STM-U — XDS560v2 시스템 추적 USB 디버그 프로브

XDS560v2는 디버그 프로브의 XDS560™ 제품군 중 최고의 성능을 가진 제품으로, 기존의 JTAG 표준(IEEE1149.1)과 cJTAG(IEEE1149.7)를 모두 지원합니다. SWD(직렬 와이어 디버그)는 지원하지 않습니다.

모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 ARM 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.

XDS560v2는 MIPI HSPT 60핀 커넥터(TI 14핀, (...)

TI.com에서 구매 불가
디버그 프로브

TMDSEMU560V2STM-UE — XDS560v2 시스템 추적 USB 및 이더넷 디버그 프로브

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

TI.com에서 구매 불가
드라이버 또는 라이브러리

SPRC100 — TMS320C55x DSP 라이브러리(DSPLIB)

The DSP Library (DSPLIB) is a collection of high-level optimized DSP function modules for the C55x DSP platform. This source-code library includes C-callable functions (ANSI-C language compatible) for general signal processing math and vector functions that have been ported to C55x DSPs. The (...)
사용 설명서: PDF
드라이버 또는 라이브러리

TELECOMLIB — 텔레콤 및 미디어 라이브러리 - TMS320C64x+ 및 TMS320C55x 프로세서를 위한 FAXLIB, VoLIB 및 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
IDE, 구성, 컴파일러 또는 디버거

CCSTUDIO Code Composer Studio integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® desktops. It can also (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

이 설계 리소스는 이러한 범주의 제품 대부분을 지원합니다.

제품 세부 정보 페이지에서 지원을 확인하십시오.

시작 다운로드 옵션
소프트웨어 코덱

C55XCODECSAUD Audio Codecs for C55x - Software and Documentation

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio and speech applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
Arm 기반 프로세서
OMAP5912 애플리케이션 프로세서
DSP(디지털 신호 프로세서)
SM320VC5507-EP EP(Enhanced Product) 저전력 C5507 고정 소수점 DSP TMS320VC5501 저전력 C55x 고정 소수점 DSP - 최대 300MHz TMS320VC5502 고정소수점 디지털 신호 프로세서 TMS320VC5503 저전력 C55x 고정 소수점 DSP - 최대 200MHz TMS320VC5505 저전력 C55x 고정 소수점 DSP - 최대 100MHz, USB, LCD 인터페이스, FFT HWA, SAR ADC TMS320VC5506 저전력 C55x 고정 소수점 DSP - 108MHz TMS320VC5507 고정소수점 디지털 신호 프로세서 TMS320VC5509A 고정소수점 디지털 신호 프로세서 TMS320VC5510A 고정 소수점 디지털 신호 프로세서
다운로드 옵션
소프트웨어 코덱

C55XCODECSPCH Speech Codecs for C55x - Software and Documentation

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio and speech applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
Arm 기반 프로세서
OMAP5912 애플리케이션 프로세서
DSP(디지털 신호 프로세서)
SM320VC5507-EP EP(Enhanced Product) 저전력 C5507 고정 소수점 DSP TMS320VC5501 저전력 C55x 고정 소수점 DSP - 최대 300MHz TMS320VC5502 고정소수점 디지털 신호 프로세서 TMS320VC5503 저전력 C55x 고정 소수점 DSP - 최대 200MHz TMS320VC5505 저전력 C55x 고정 소수점 DSP - 최대 100MHz, USB, LCD 인터페이스, FFT HWA, SAR ADC TMS320VC5506 저전력 C55x 고정 소수점 DSP - 108MHz TMS320VC5507 고정소수점 디지털 신호 프로세서 TMS320VC5509A 고정소수점 디지털 신호 프로세서 TMS320VC5510A 고정 소수점 디지털 신호 프로세서
다운로드 옵션
시뮬레이션 모델

VC5503 GHH BSDL Model

SPRM208.ZIP (6 KB) - BSDL Model
시뮬레이션 모델

VC5503 GHH IBIS Model

SPRM474.ZIP (88 KB) - IBIS Model
시뮬레이션 모델

VC5503 PGE BSDL Model

SPRM209.ZIP (6 KB) - BSDL Model
시뮬레이션 모델

VC5503 PGE IBIS Model

SPRM475.ZIP (87 KB) - IBIS Model
패키지 CAD 기호, 풋프린트 및 3D 모델
LQFP (PGE) 144 Ultra Librarian
NFBGA (ZAY) 179 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

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품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

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