제품 상세 정보

Configuration 2:1 SPDT Number of channels 4 Power supply voltage - single (V) 5, 12, 16, 20, 36, 44 Power supply voltage - dual (V) +/-10, +/-15, +/-18, +/-22, +/-5 Protocols Analog Ron (typ) (Ω) 3.5 CON (typ) (pF) 76 ON-state leakage current (max) (µA) 0.008 Supply current (typ) (µA) 45 Bandwidth (MHz) 100 Operating temperature range (°C) -40 to 125 Features 1.8-V compatible control inputs, Break-before-make, Fail-safe logic, Integrated pulldown resistor on logic pin Input/output continuous current (max) (mA) 400 Rating Catalog Drain supply voltage (max) (V) 44 Supply voltage (max) (V) 44 Negative rail supply voltage (max) (V) -44
Configuration 2:1 SPDT Number of channels 4 Power supply voltage - single (V) 5, 12, 16, 20, 36, 44 Power supply voltage - dual (V) +/-10, +/-15, +/-18, +/-22, +/-5 Protocols Analog Ron (typ) (Ω) 3.5 CON (typ) (pF) 76 ON-state leakage current (max) (µA) 0.008 Supply current (typ) (µA) 45 Bandwidth (MHz) 100 Operating temperature range (°C) -40 to 125 Features 1.8-V compatible control inputs, Break-before-make, Fail-safe logic, Integrated pulldown resistor on logic pin Input/output continuous current (max) (mA) 400 Rating Catalog Drain supply voltage (max) (V) 44 Supply voltage (max) (V) 44 Negative rail supply voltage (max) (V) -44
TSSOP (PW) 20 41.6 mm² 6.5 x 6.4 WQFN (RRQ) 20 16 mm² 4 x 4
  • Latch-up immune
  • Dual supply range: ±4.5 V to ±22 V
  • Single supply range: 4.5 V to 44 V
  • Low on-resistance: 3 Ω
  • Low charge injection: 3 pC
  • High current support: 400 mA (maximum)
  • –40°C to +125°C operating temperature
  • 1.8 V logic compatible inputs
  • Fail-safe logic
  • Rail-to-rail operation
  • Bidirectional signal path
  • Break-before-make switching
  • Latch-up immune
  • Dual supply range: ±4.5 V to ±22 V
  • Single supply range: 4.5 V to 44 V
  • Low on-resistance: 3 Ω
  • Low charge injection: 3 pC
  • High current support: 400 mA (maximum)
  • –40°C to +125°C operating temperature
  • 1.8 V logic compatible inputs
  • Fail-safe logic
  • Rail-to-rail operation
  • Bidirectional signal path
  • Break-before-make switching

The TMUX7234 is a complementary metal-oxide semiconductor (CMOS) multiplexer with latch-up immunity. The TMUX7234 contains four independently controlled SPDT switches with an EN pin to enable or disable all four channels. The device supports single supply (4.5 V to 44 V), dual supplies (±4.5 V to ±22 V), or asymmetric supplies (such as VDD = 12 V, VSS = –5 V). The TMUX7234 supports bidirectional analog and digital signals on the source (Sx) and drain (D) pins ranging from VSS to VDD.

All logic control inputs support logic levels from 1.8 V to VDD, ensuring both TTL and CMOS logic compatibility when operating in the valid supply voltage range. Fail-Safe Logic circuitry allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage.

The TMUX72xx family provides latch-up immunity, preventing undesirable high current events between parasitic structures within the device typically caused by overvoltage events. A latch-up condition typically continues until the power supply rails are turned off and can lead to device failure. The latch-up immunity feature allows the TMUX72xx family of switches and multiplexers to be used in harsh environments.

The TMUX7234 is a complementary metal-oxide semiconductor (CMOS) multiplexer with latch-up immunity. The TMUX7234 contains four independently controlled SPDT switches with an EN pin to enable or disable all four channels. The device supports single supply (4.5 V to 44 V), dual supplies (±4.5 V to ±22 V), or asymmetric supplies (such as VDD = 12 V, VSS = –5 V). The TMUX7234 supports bidirectional analog and digital signals on the source (Sx) and drain (D) pins ranging from VSS to VDD.

All logic control inputs support logic levels from 1.8 V to VDD, ensuring both TTL and CMOS logic compatibility when operating in the valid supply voltage range. Fail-Safe Logic circuitry allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage.

The TMUX72xx family provides latch-up immunity, preventing undesirable high current events between parasitic structures within the device typically caused by overvoltage events. A latch-up condition typically continues until the power supply rails are turned off and can lead to device failure. The latch-up immunity feature allows the TMUX72xx family of switches and multiplexers to be used in harsh environments.

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기술 자료

star =TI에서 선정한 이 제품의 인기 문서
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4개 모두 보기
유형 직함 날짜
* Data sheet TMUX7234 44 V, Low Ron, 2:1, 4 Channel Precision Switches with Latch-Up Immunity and 1.8 V Logic datasheet (Rev. G) PDF | HTML 2024/07/18
Application note How to Handle High Voltage Common Mode Applications using Multiplexers PDF | HTML 2022/10/03
Application note Using Latch Up Immune Multiplexers to Help Improve System Reliability (Rev. A) 2021/09/20
Application brief Precision Multiplexers Reducing Barriers in an Industrial Environment PDF | HTML 2021/05/21

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

TMUXRTJ-RRQEVM — 20핀 RTJ 및 RRQ QFN 패키지용 일반 TMUX 평가 모듈

TMUXRTJ-RRQEVM을 사용하면 20핀 RTJ 또는 RRQ 패키지(QFN)를 사용하고 고전압 작동에 맞게 정격 조정된 TI의 TMUX 제품 라인의 빠른 프로토타이핑 및 DC 특성화가 가능합니다.

사용 설명서: PDF | HTML
TI.com에서 구매 불가
인터페이스 어댑터

LEADED-ADAPTER1 — TI의 5, 8, 10, 16 및 24핀 리드 패키지의 빠른 테스트를 위한 DIP 헤더 어댑터에 대한 표면 실장

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

사용 설명서: PDF
TI.com에서 구매 불가
인터페이스 어댑터

LEADLESS-ADAPTER1 — TI의 6, 8, 10, 12, 14, 16 및 20핀 리드 없는 패키지의 테스트를 위한 DIP 헤더 어댑터에 대한 표면 실장

The EVM-LEADLESS1 board allows for quick testing and bread boarding of TI's common leadless packages.  The board has footprints to convert TI's DRC, DTP, DQE, RBW, RGY, RSE, RSV, RSW RTE, RTJ, RUK , RUC, RUG, RUM,RUT and YZP surface mount packages to 100mil DIP headers.
사용 설명서: PDF
TI.com에서 구매 불가
시뮬레이션 모델

TMUX7234 IBIS Model

SCDM264.ZIP (52 KB) - IBIS Model
시뮬레이션 모델

TMUX72XX-8SW - TMUX723X PSPICE Model

SCDM303.ZIP (29 KB) - PSpice Model
패키지 CAD 기호, 풋프린트 및 3D 모델
TSSOP (PW) 20 Ultra Librarian
WQFN (RRQ) 20 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

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