TXS0102V

활성

오픈 드레인 및 푸시-풀 애플리케이션을 위한 2비트 양방향 레벨 시프터

제품 상세 정보

Technology family TXS Applications I2C, MDIO Bits (#) 2 Data rate (max) (Mbps) 24 High input voltage (min) (V) 1.45 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 IOH (max) (mA) 0 IOL (max) (mA) 0 Supply current (max) (µA) 10 Features Edge rate accelerator, Output enable, Partial power down (Ioff), Vcc isolation Input type Transmission Gate Output type 3-State, Transmission Gate Rating Catalog Operating temperature range (°C) -40 to 85
Technology family TXS Applications I2C, MDIO Bits (#) 2 Data rate (max) (Mbps) 24 High input voltage (min) (V) 1.45 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 IOH (max) (mA) 0 IOL (max) (mA) 0 Supply current (max) (µA) 10 Features Edge rate accelerator, Output enable, Partial power down (Ioff), Vcc isolation Input type Transmission Gate Output type 3-State, Transmission Gate Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DCT) 8 11.8 mm² 2.95 x 4 VSSOP (DCU) 8 6.2 mm² 2 x 3.1
  • No direction-control signal needed
  • Maximum data rates:
    • 24 Mbps (push pull)
    • 2 Mbps (open drain)
  • Available in the Texas Instruments NanoStar™ integrated circuit package
  • 1.65V to 3.6V on A port and 2.3V to 5.5V on B port (VCCA ≤ VCCB)
  • VCC isolation feature: if either VCC input is at GND, both ports are in the High-Impedance state
  • No power-supply sequencing required: either VCCA or VCCB can be ramped first
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • A port:
      • 2000V Human-Body Model (A114-B)
      • 500V Charged-Device Model (C101)
    • B port:
      • 5000V Human-Body Model (A114-B)
      • 500V Charged-Device Model (C101)
  • No direction-control signal needed
  • Maximum data rates:
    • 24 Mbps (push pull)
    • 2 Mbps (open drain)
  • Available in the Texas Instruments NanoStar™ integrated circuit package
  • 1.65V to 3.6V on A port and 2.3V to 5.5V on B port (VCCA ≤ VCCB)
  • VCC isolation feature: if either VCC input is at GND, both ports are in the High-Impedance state
  • No power-supply sequencing required: either VCCA or VCCB can be ramped first
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • A port:
      • 2000V Human-Body Model (A114-B)
      • 500V Charged-Device Model (C101)
    • B port:
      • 5000V Human-Body Model (A114-B)
      • 500V Charged-Device Model (C101)

This two-bit non-inverting translator is a bidirectional voltage-level translator and can be used to establish digital switching compatibility between mixed-voltage systems. It uses two separate configurable power-supply rails, with the A ports supporting operating voltages from 1.65V to 3.6V while it tracks the VCCA supply, and the B ports supporting operating voltages from 2.3V to 5.5V while it tracks the VCCB supply. This allows the support of both lower and higher logic signal levels while providing bidirectional translation capabilities between any of the 1.8V, 2.5V, 3.3V, and 5V voltage nodes.

When the output-enable (OE) input is low, all I/Os are placed in the high-impedance state, which significantly reduces the power-supply quiescent current consumption.

To put the device in the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the current-sourcing capability of the driver determines the minimum value of the resistor.

This two-bit non-inverting translator is a bidirectional voltage-level translator and can be used to establish digital switching compatibility between mixed-voltage systems. It uses two separate configurable power-supply rails, with the A ports supporting operating voltages from 1.65V to 3.6V while it tracks the VCCA supply, and the B ports supporting operating voltages from 2.3V to 5.5V while it tracks the VCCB supply. This allows the support of both lower and higher logic signal levels while providing bidirectional translation capabilities between any of the 1.8V, 2.5V, 3.3V, and 5V voltage nodes.

When the output-enable (OE) input is low, all I/Os are placed in the high-impedance state, which significantly reduces the power-supply quiescent current consumption.

To put the device in the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the current-sourcing capability of the driver determines the minimum value of the resistor.

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유형 직함 날짜
* Data sheet TXS0102V 2-Bit Bi-Directional, Level-Shifting, Voltage Translator for Open-Drain and Push-Pull Applications datasheet PDF | HTML 2024/06/24

설계 및 개발

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평가 보드

5-8-LOGIC-EVM — 5핀~8핀 DCK, DCT, DCU, DRL 및 DBV 패키지용 일반 논리 평가 모듈

5~8핀 수의 DCK, DCT, DCU, DRL 또는 DBV 패키지가 있는 모든 디바이스를 지원하도록 설계된 유연한 EVM.
사용 설명서: PDF
TI.com에서 구매 불가
평가 보드

TXS-EVM — Translator family evaluation module for single-, dual-, quad- and octal-channel devices

The TXS-EVM is designed to support single, dual, quad and octal channel TXS devices. The TXS devices belong to the auto bidirectional voltage level translation family with an operating voltage between 1.2V and 5.5 V designed to support various generic voltage level translation applications across (...)

사용 설명서: PDF | HTML
TI.com에서 구매 불가

많은 TI 레퍼런스 설계에는 TXS0102V이(가) 포함됩니다.

레퍼런스 디자인 선택 툴을 사용하여 애플리케이션 및 매개 변수에 가장 적합한 설계를 검토하고 식별할 수 있습니다.

패키지 CAD 기호, 풋프린트 및 3D 모델
SSOP (DCT) 8 Ultra Librarian
VSSOP (DCU) 8 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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