홈 데이터 컨버터 통합 및 특수 기능 데이터 컨버터 CCD 및 CIS 이미징 AFE
홈
데이터 컨버터
통합 및 특수 기능 데이터 컨버터
CCD 및 CIS 이미징 AFE

VSP5611

활성

16비트, 50MSPS 4채널 이미징 아날로그 프론트 엔드

지금 주문
데이터 시트

VSP5611

활성
데이터 시트 지금 주문

제품 상세 정보

Resolution (Bits) 16 Number of channels 4 Sample rate (Msps) 50 Gain (min) (dB) -6 Gain (max) (dB) 17 Pd (typ) (mW) 426 Supply voltage (max) (V) 3.3 Operating temperature range (°C) 0 to 85 Output data format CMOS Parallel, LVDS Rating Catalog
Resolution (Bits) 16 Number of channels 4 Sample rate (Msps) 50 Gain (min) (dB) -6 Gain (max) (dB) 17 Pd (typ) (mW) 426 Supply voltage (max) (V) 3.3 Operating temperature range (°C) 0 to 85 Output data format CMOS Parallel, LVDS Rating Catalog
VQFN (RSH) 56 49 mm² 7 x 7
  • Four-Channel CCD/CMOS Signal: 2-Channel, 3-Channel, and 4-Channel Selectable
  • Power Supply: 3.3 V Only, Typ
    (Built-in LDO, 3.3 V to 1.8 V)
  • Maximum Conversion Rate:
    • VSP5610: 35 MSPS
    • VSP5611: 50 MSPS
    • VSP5612: 70 MSPS
  • 16-Bit Resolution
  • CDS/SH Selectable
  • Maximum Input Signal Range: 2.0 V
  • Analog and Digital Hybrid Gain:
    • Analog Gain: 0.5 V/V to 3.5 V/V in
      3/64-V/V Steps
    • Digital Gain: 1 V/V to 2 V/V in
      1/256-V/V Steps
  • Offset Correction DAC: ±250 mV, 8-Bit
  • Standard LVDS/CMOS Selectable Output:
    • LVDS:Data Channel: 2-Channel, 3-ChannelClock Channel: 1-Channel8-Bit/7-Bit Serializer Selectable
    • CMOS: 4 Bits × 4, 8 Bits × 2
  • Timing Generator:
    • Fast Transfer Clock: Eight Signals
    • Slow Transfer Clock: Six Signals
  • Timing Adjustment Resolution: tMCLK/48
  • Input Clamp/Input Reference Level Internal/External Selectable
  • Reference DAC: 0.5 V, 1.1 V, 1.5 V, 2 V
  • SPI™: Three-Wire Serial
  • GPIO: Four-Port
  • APPLICATIONS
    • Copiers
    • Facsimile Machines
    • Scanners

    • SPI is a trademark of Motorola.
    All other trademarks are the property of their respective owners.
    • Four-Channel CCD/CMOS Signal: 2-Channel, 3-Channel, and 4-Channel Selectable
    • Power Supply: 3.3 V Only, Typ
      (Built-in LDO, 3.3 V to 1.8 V)
    • Maximum Conversion Rate:
      • VSP5610: 35 MSPS
      • VSP5611: 50 MSPS
      • VSP5612: 70 MSPS
    • 16-Bit Resolution
    • CDS/SH Selectable
    • Maximum Input Signal Range: 2.0 V
    • Analog and Digital Hybrid Gain:
      • Analog Gain: 0.5 V/V to 3.5 V/V in
        3/64-V/V Steps
      • Digital Gain: 1 V/V to 2 V/V in
        1/256-V/V Steps
    • Offset Correction DAC: ±250 mV, 8-Bit
    • Standard LVDS/CMOS Selectable Output:
      • LVDS:Data Channel: 2-Channel, 3-ChannelClock Channel: 1-Channel8-Bit/7-Bit Serializer Selectable
      • CMOS: 4 Bits × 4, 8 Bits × 2
    • Timing Generator:
      • Fast Transfer Clock: Eight Signals
      • Slow Transfer Clock: Six Signals
    • Timing Adjustment Resolution: tMCLK/48
    • Input Clamp/Input Reference Level Internal/External Selectable
    • Reference DAC: 0.5 V, 1.1 V, 1.5 V, 2 V
    • SPI™: Three-Wire Serial
    • GPIO: Four-Port
  • APPLICATIONS
    • Copiers
    • Facsimile Machines
    • Scanners

    • SPI is a trademark of Motorola.
    All other trademarks are the property of their respective owners.

    The VSP5610/11/12 are high-speed, high-performance, 16-bit analog-to-digital-converters (ADCs) that have four independent sampling circuit channels for multi-output charge-coupled device (CCD) and complementary metal oxide semiconductor (CMOS) line sensors. Pixel data from the sensor are sampled by the sample/hold (SH) or correlated double sampler (CDS) circuit, and are then converted to digital data by an ADC. Data output is selectable in low-voltage differential signaling (LVDS) or CMOS modes.

    The VSP5610/11/12 include a programmable gain to support the pixel level inflection caused by luminance. The integrated digital-to-analog-converter (DAC) can be used to adjust the offset level for the analog input signal. Furthermore, the timing generator (TG) is integrated in these devices for the control of sensor operation.

    The VSP5610/11/12 use 1.65 V to 1.95 V for the core voltage and 3.0 V to 3.6 V for I/Os. The core voltage is supplied by a built-in low-dropout regulator (LDO).

    The VSP5610/11/12 are high-speed, high-performance, 16-bit analog-to-digital-converters (ADCs) that have four independent sampling circuit channels for multi-output charge-coupled device (CCD) and complementary metal oxide semiconductor (CMOS) line sensors. Pixel data from the sensor are sampled by the sample/hold (SH) or correlated double sampler (CDS) circuit, and are then converted to digital data by an ADC. Data output is selectable in low-voltage differential signaling (LVDS) or CMOS modes.

    The VSP5610/11/12 include a programmable gain to support the pixel level inflection caused by luminance. The integrated digital-to-analog-converter (DAC) can be used to adjust the offset level for the analog input signal. Furthermore, the timing generator (TG) is integrated in these devices for the control of sensor operation.

    The VSP5610/11/12 use 1.65 V to 1.95 V for the core voltage and 3.0 V to 3.6 V for I/Os. The core voltage is supplied by a built-in low-dropout regulator (LDO).
    filter 기타 CCD 및 CIS 이미징 AFE 찾기
    다운로드

    기술 자료

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    유형 직함 날짜
    * Data sheet 16-Bit, 4-Channel, CCD/CMOS Sensor Analog Front-End With Timing Generator datasheet 2011/06/28

    주문 및 품질

    포함된 정보:
    • RoHS
    • REACH
    • 디바이스 마킹
    • 납 마감/볼 재질
    • MSL 등급/피크 리플로우
    • MTBF/FIT 예측
    • 물질 성분
    • 인증 요약
    • 지속적인 신뢰성 모니터링
    포함된 정보:
    • 팹 위치
    • 조립 위치

    지원 및 교육

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