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CDC7005

現行

可將參考時脈與 VCXO 同步的高性能、低相位雜訊、低偏斜時脈同步器

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產品規格表

CDC7005

現行
產品規格表 立即訂購

產品詳細資料

Function Clock generator Number of outputs 5 Output frequency (max) (MHz) 800 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS, LVPECL Output type LVPECL Operating temperature range (°C) -40 to 85 Features Op-amp for active loop filter, Programmable delay Rating Catalog
Function Clock generator Number of outputs 5 Output frequency (max) (MHz) 800 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS, LVPECL Output type LVPECL Operating temperature range (°C) -40 to 85 Features Op-amp for active loop filter, Programmable delay Rating Catalog
BGA (ZVA) 64 64 mm² 8 x 8 VQFN (RGZ) 48 49 mm² 7 x 7
  • High Performance 1:5 PLL Clock Synchronizer
  • Two Clock Inputs: VCXO_IN Clock Is Synchronized to REF_IN Clock
  • Synchronizes Frequencies up to 800 MHz (VCXO_IN)
  • Supports Five Differential LVPECL Outputs
  • Each Output Frequency Is Selectable by x1, /2, /4, /8, /16
  • All Outputs Are Synchronized
  • Integrated Low-Noise OPA for External Low-Pass Filter
  • Efficient Jitter Screening From Low PLL Loop Bandwidth
  • Low-Phase Noise Characteristic
  • Programmable Delay for Phase Adjustments
  • Predivider Loop BW Adjustment
  • SPI Controllable Division Setting
  • Power-Up Control Forces LVPECL Outputs to 3-State at VCC <1.5 V
  • 3.3-V Power Supply
  • Packaged In 64-Pin BGA (0,8 mm Pitch - ZVA) or 48-Pin QFN (RGZ)
  • Industrial Temperature Range –40°C to 85°C
  • High Performance 1:5 PLL Clock Synchronizer
  • Two Clock Inputs: VCXO_IN Clock Is Synchronized to REF_IN Clock
  • Synchronizes Frequencies up to 800 MHz (VCXO_IN)
  • Supports Five Differential LVPECL Outputs
  • Each Output Frequency Is Selectable by x1, /2, /4, /8, /16
  • All Outputs Are Synchronized
  • Integrated Low-Noise OPA for External Low-Pass Filter
  • Efficient Jitter Screening From Low PLL Loop Bandwidth
  • Low-Phase Noise Characteristic
  • Programmable Delay for Phase Adjustments
  • Predivider Loop BW Adjustment
  • SPI Controllable Division Setting
  • Power-Up Control Forces LVPECL Outputs to 3-State at VCC <1.5 V
  • 3.3-V Power Supply
  • Packaged In 64-Pin BGA (0,8 mm Pitch - ZVA) or 48-Pin QFN (RGZ)
  • Industrial Temperature Range –40°C to 85°C

The CDC7005 is a high-performance, low-phase noise, and low-skew clock synchronizer and jitter cleaner that synchronizes the voltage controlled crystal oscillator (VCXO) frequency to the reference clock. The programmable predividers M and N give a high flexibility to the frequency ratio of the reference clock to VCXO: VCXO_IN/REF_IN = (NxP)/M. The VCXO_IN clock operates up to 800 MHz. Through the selection of external VCXO and loop filter components, the PLL loop bandwidth and damping factor can be adjusted to meet different system requirements. Each of the five differential LVPECL outputs is programmable by the serial peripheral interface (SPI). The SPI allows individual control of frequency and enable/disable state of each output. The device operates in 3.3-V environment. The built-in latches ensure that all outputs are synchronized.

The CDC7005 is characterized for operation from –40°C to 85°C.

The CDC7005 is a high-performance, low-phase noise, and low-skew clock synchronizer and jitter cleaner that synchronizes the voltage controlled crystal oscillator (VCXO) frequency to the reference clock. The programmable predividers M and N give a high flexibility to the frequency ratio of the reference clock to VCXO: VCXO_IN/REF_IN = (NxP)/M. The VCXO_IN clock operates up to 800 MHz. Through the selection of external VCXO and loop filter components, the PLL loop bandwidth and damping factor can be adjusted to meet different system requirements. Each of the five differential LVPECL outputs is programmable by the serial peripheral interface (SPI). The SPI allows individual control of frequency and enable/disable state of each output. The device operates in 3.3-V environment. The built-in latches ensure that all outputs are synchronized.

The CDC7005 is characterized for operation from –40°C to 85°C.
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類型 標題 日期
* Data sheet 3.3-V High Performance Clock Synthesizer & Jitter Cleaner datasheet (Rev. L) 2009年 6月 4日
Application brief Using The CDC7005 as a 1:5 PECL Buffer w/Programmable Divider Ratio (Rev. B) 2009年 12月 15日
Application note Basics of the CDC7005 Hold Function 2006年 4月 13日
EVM User's guide CDC7005 (BGA Package) EVM (Rev. E) 2006年 3月 28日
User guide CDC7005 (QFN Package) Evaluation Module Manual (Rev. B) 2006年 3月 28日
EVM User's guide CDC7005 (BGA Package) EVM (Rev. D) 2005年 12月 29日
User guide CDC7005 (QFN Package) Evaluation Module Manual (Rev. A) 2005年 12月 29日
User guide CDC7005 (QFN Package) Evaluation Module Manual 2005年 7月 20日
Application note Phase Noise (Jitter) Performance of CDC7005 With Different VCXOs (Rev. A) 2005年 7月 19日
EVM User's guide CDC7005EVM User Guide (Rev. C) 2005年 2月 17日
Application note Open Loop Phase-Noise Performance of CDC7005 at Various Frequencies 2004年 12月 17日
User guide TSW2000 Receive Clock JItter Cleaning EVM 2004年 6月 28日
Application note Implementing a CDC7005 Low Jitter Clock Solution for HIgh Speed High IF ADC Dev 2004年 6月 25日
Product overview ADS5500 + CDC7005 Product Bulletin 2004年 6月 23日
Product overview TSW2000: TLK1201A & CDC7005 2004年 6月 23日
Application note General Guidelines: CDC7005 as a Clock Synthesizer and Jitter Cleaner (Rev. A) 2003年 12月 16日
Application note General Guidelines: CDC7005 as a Clock Synthesizer and Jitter Cleaner 2003年 3月 21日

設計與開發

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支援軟體

SCAC037 — CDC7005 SPI Software with Labview 8.0 Runtime Engine

支援產品和硬體

支援產品和硬體

產品
時鐘產生器
CDC7005 — 可將參考時脈與 VCXO 同步的高性能、低相位雜訊、低偏斜時脈同步器
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模擬型號

CDC7005 IBIS Model

SCAC033.ZIP (34 KB) - IBIS Model
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物料清單

TSW1000 EVM Bill of Materials

SLWR028.ZIP (166 KB)
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計算工具

CDC-CDCM7005-CALC — CDC7005 和 CDCM7005 PLL 迴路頻寬計算機

This tool helps to determine the right divider values (M, N & P) and to choose the filter type and components. This calculator will help to find out the appropriate loop bandwidth, phase margin, jitter peaking, etc. just varying the loop parameters like PFD frequency, filter components, Charge pump (...)
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Gerber 檔案

CDC7005 EVM QFN Gerber Files

SCAC066.ZIP (537 KB)
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Gerber 檔案

TSW1000 EVM Gerber Files

SLWC050.ZIP (532 KB)
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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
要求
封裝 針腳 CAD 符號、佔位空間與 3D 模型
BGA (ZVA) 64 Ultra Librarian
VQFN (RGZ) 48 Ultra Librarian
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