CDCE62005
- Superior Performance:
- Low Noise Clock Generator: 550 fs rms typical (10 kHz to 20 MHz Integration Bandwidth),
FC = 100 MHz - Low Noise Jitter Cleaner: 2.6 ps rms typical (10 kHz to 20 MHz Integration Bandwidth),
FC = 100 MHz
- Low Noise Clock Generator: 550 fs rms typical (10 kHz to 20 MHz Integration Bandwidth),
- Flexible Frequency Planning:
- 5 Fully Configurable Outputs: LVPECL, LVDS, LVCMOS and Special High Swing Output Modes
- Unique Dual-VCO Architecture Supports a Wide Tuning Range: 1.750 GHz to 2.356 GHz
- Output Frequency Ranges from 4.25 MHz to 1.175 GHz in Synthesizer Mode
- Output Frequency up to 1.5 GHz in Fan-Out Mode
- Independent Coarse Skew Control on all Outputs
- High Flexibility:
- Integrated EEPROM Determines Device Configuration at Power-up
- Smart Input Multiplexer Automatically Switches Between One of Three Reference Inputs
- 7-mm × 7-mm 48-Pin VQFN Package (RGZ)
- –40°C to +85°C Temperature Range
The CDCE62005 is a high performance clock generator and distributor featuring low output jitter, a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62005 achieves jitter performance well under 1 ps RMS (10 kHz to 20 MHz integration bandwidth).
The CDCE62005 incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (up to 1.5 GHz) and skew relationship via a programmable delay block (note that frequency range depends on operational mode and output format selected). If all outputs are configured in single-ended mode (for example, LVCMOS), the CDCE62005 supports up to ten outputs. Each output can select one of four clock sources to condition and distribute including any of the three clock inputs or the output of the frequency synthesizer. The input block includes two universal differential inputs which support frequencies in the range of 40 kHz to 500 MHz and an auxiliary input that can be configured to connect to an external crystal via an on chip oscillator block.
The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the synthesizer reference via the SPI interface. In automatic mode, the input multiplexer will automatically select between the highest priority input clock available.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | CDCE62005 3:5 Clock Generator, Jitter Cleaner with Integrated Dual VCOs datasheet (Rev. G) | PDF | HTML | 2016年 5月 23日 |
| User guide | TSW6011EVM Quick Start Guide (Rev. D) | 2016年 8月 17日 | ||
| Application note | Clocking Design Guidelines: Unused Pins | 2015年 11月 19日 | ||
| Application note | Effects of Clock Spur on High Speed DAC Performance (Rev. A) | 2015年 5月 18日 | ||
| Application note | Effects of Clock Noise on High Speed DAC Performance | 2012年 11月 8日 | ||
| Application note | Phase Noise Performance and Loop Bandwidth Optimization of CDCE62005 | 2011年 8月 11日 | ||
| Application note | CDCE62005 Application Report | 2008年 11月 21日 | ||
| Application note | LAN & WAN clock generation and muxing using the CDCE62005 | 2008年 11月 19日 | ||
| User guide | Low Phase Noise Clock Evaluation Module — up to 1.5 Ghz | 2008年 11月 11日 | ||
| Application note | CDCE62005 Phase Noise and Jitter Cleaning Performance | 2008年 9月 5日 | ||
| Application note | CDCE62005 as Clock Solution for High-Speed ADCs | 2008年 9月 4日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
CDCE62005EVM — CDCE62005EVM 評估模組
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SCAC105 — CDCE62005 EVM Control Software Installer
支援產品和硬體
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TIDEP0036 — 使用 TMS320C6657 實作高效率 OPUS 轉碼器解決方案的參考設計
TIDA-00078 — 具有 I/Q 校正的直接降壓轉換系統
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。