CDCE6214Q1TM
- AEC-Q100 qualified for automotive applications
- Temperature grade 2: –40°C to +105°C
- Functional Safety-Capable
- Configurable high performance, low-power, frac-N PLL with RMS jitter with spurs (12 kHz – 20 MHz, F out > 100 MHz) as:
- Integer mode:
- Differential output: 350 fs typical, 600 fs maximum
- LVCMOS output: 1.05 ps typical, 1.5 ps maximum
- Fractional mode:
- Differential output: 1.7 ps typical, 2.1 ps maximum
- LVCMOS output: 2.0 ps typical, 4.0 ps maximum
- Integer mode:
- Supports PCIe Gen1/2/3/4 with SSC and Gen 1/2/3/4/5 without SSC
- Internal VCO: 2.335 GHz to 2.625 GHz
- Typical power consumption: 65 mA for 4-output channel, 23 mA for 1-output channel.
- Universal clock input, two reference inputs for redundancy
- Differential AC-coupled or LVCMOS: 10 MHz to 200 MHz
- Crystal: 10 MHz to 50 MHz
- Flexible output clock distribution
- Four channel dividers: Up to five unique output frequencies from 24 kHz to 328.125 MHz
- Combination of LVDS-like, LP-HCSL or LVCMOS outputs on OUT0 – OUT4 pins
- Glitchless output divider switching and output channel synchronization
- Individual output enable through active-low GPIO and register
- Frequency margining options
- DCO mode: frequency increment/decrement with 10ppb or less step-size
- Fully-integrated, configurable loop bandwidth: 100 kHz to 1.6 MHz
- Single or mixed supply for level translation: 1.8 V, 2.5 V, 3.3 V
- Configurable GPIOs and flexible configuration options
- I 2C-compatible interface: up to 400 kHz
- Integrated EEPROM with two pages and external select pin. In-situ programming allowed.
- Supports 100-Ω systems
- Low electromagnetic emissions
- Small footprint: 24-pin VQFN (4 mm × 4 mm)
The CDCE6214Q1TM is a 4-channel, ultra-low power, medium grade jitter, clock generator for automotive application that can generate five independent clock outputs selectable between various modes of drivers. The input source can be a single-ended or differential input clock source, or a crystal. The CDCE6214Q1TM features a frac-N PLL to synthesize unrelated base frequency from any input frequency.
技術文件
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檢視所有 3 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | CDCE6214Q1TM Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, Two Inputs, and Internal EEPROM datasheet | PDF | HTML | 2023年 6月 27日 |
| Application note | Clocking for PCIe Applications | PDF | HTML | 2023年 11月 28日 | |
| Functional safety information | CDCE6214-Q1 Functional Safety, FIT Rate, Failure Mode Distribution and Pin FMA | PDF | HTML | 2021年 4月 15日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
開發板
CDCE6214-Q1EVM — 4 個差分和 1 個 LVCMOS 輸出時脈產生器評估模組
The CDCE6214-Q1 evalution module (EVM) is an evaluation platform for the CDCE6214-Q1 ultra-low power clock generator. This
evaluation module provides an USB-based interface to access the I2C bus to communicate with the CDCE6214-Q1. Pin control mode can set the device in a specific operation
evaluation module provides an USB-based interface to access the I2C bus to communicate with the CDCE6214-Q1. Pin control mode can set the device in a specific operation
使用指南: PDF
設計工具
CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體
Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGE) | 24 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。