SM320C80
- Single-Chip Parallel Multiple Instruction/Multiple Data (MIMD) Digital Signal Processor (DSP)
- More Than Two Billion RISC-Equivalent Operations per Second
- Master Processor (MP)
- 32-Bit Reduced Instruction Set Computing (RISC) Processor
- IEEE-754 Floating-Point Capability
- 4K-Byte Instruction Cache
- 4K-Byte Data Cache
- Four Parallel Processors (PP)
- 32-Bit Advanced DSPs
- 64-Bit Opcode Provides Many Parallel Operations per Cycle
- 2K-Byte Instruction Cache and 8K-Byte Data RAM per PP
- Transfer Controller (TC)
- 64-Bit Data Transfers
- Up to 400 Megabytes per Second (MBps) Transfer Rate
- 32-Bit Addressing
- Direct DRAM/VRAM Interface With Dynamic Bus Sizing
- Intelligent Queuing and Cycle Prioritization
- Video Controller (VC)
- Provides Video Timing and Video Random-Access Memory (VRAM) Control
- Dual-Frame Timers for Two Simultaneous Image-Capture and/or Display Systems
- Big- or Little-Endian Operation
- 50K-Byte On-Chip RAM
- 4G-Byte Address Space
- 20-ns Cycle Time
- 3.3-V Operation
- IEEE Standard 1149.1
Test Access Port (JTAG) - Operating Temperature Range
–55°C to 125°C - M-Temperature
–40°C to 85°C - A-Temperature
IEEE Standard 1149.1–1990, IEEE Standard Test Access Port and Boundary-Scan Architecture
The SMJ320C80 is a single-chip, MIMD parallel processor capable of performing over two billion operations per second. It consists of a 32-bit RISC master processor with a 100-MFLOPS (million floating-point operations per second) IEEE floating-point unit, four 32-bit parallel processing digital signal processors (DSPs), a transfer controller with up to 400-MBps off-chip transfer rate, and a video controller. All the processors are coupled tightly through an on-chip crossbar that provides shared access to on-chip RAM. This performance and programmability make the ’C80 ideally suited for video, imaging, and high-speed telecommunications applications.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | SMJ320C80 Digital Signal Processor datasheet (Rev. B) | 2002年 6月 30日 | |
| More literature | SM320C80/SMJ320C80 (Rev. C) | 2000年 8月 7日 | ||
| User guide | TMS320C8x Emulator Installation Guide (Rev. A) | 1997年 2月 1日 | ||
| Application note | Modified Goertzel Algorithm in DTMF Detection Using the TMS320C80 DSP | 1996年 6月 1日 | ||
| Application note | Acoustic Echo Cancellation Algorithms and Implementation on the TMS320C80 | 1996年 5月 1日 | ||
| User guide | TMS320C80 to TMS320C82 Software Compatibility User's Guide | 1995年 11月 1日 | ||
| Application note | TMS320C8x System-Level Synopsis (Rev. B) | 1995年 9月 1日 | ||
| User guide | TMS320C8x (MVP) Video Controller User's Guide (Rev. A) | 1995年 1月 1日 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| CFP (HFH) | 320 | Ultra Librarian |
| CPGA (GF) | 305 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點