產品詳細資料

Operating system Integrity, Linux, Neutrino, PrOS, Windows Embedded CE Rating Catalog Operating temperature range (°C) 0 to 85
Operating system Integrity, Linux, Neutrino, PrOS, Windows Embedded CE Rating Catalog Operating temperature range (°C) 0 to 85
NFBGA (ZCE) 337 169 mm² 13 x 13
  • Highlights
    • High-Performance Digital Media System-On-Chip (DMSoC)
    • Up to 216-MHz ARM926EJ-STM Clock Rate
    • Digital HDTV (720p/1080i) output for connection to external encoder
    • Video Processing Subsystem
      • Hardware IPIPE for Real-Time Image Processing
      • Up to 14-bit CCD/CMOS Digital Interface
      • Histogram Module
      • Resize Image 1/16x to 8x
      • Hardware On-Screen Display
      • Up to 75-MHz Pixel Clock
      • Composite NTSC/PAL video encoder output
    • Peripherals include DDR and mDDR SDRAM, 2 MMC/SD/SDIO and SmartMedia Flash Card Interfaces, USB 2.0, 3 UARTs and 3 SPIs
    • Enhanced Direct-Memory-Access (EDMA)
    • Configurable Power-Saving Modes
    • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART
    • 3.3-V and 1.8-V I/O, 1.3-V Core
    • Debug Interface Support
    • Up to 104 General-Purpose I/O (GPIO) Pins
    • 337-Pin Ball Grid Array at 65 nm Process Technology
  • High-Performance Digital Media System-on-Chip
    • 135-, 216-MHz ARM926EJ-S™ Clock Rate
    • Fully Software-Compatible With ARM™
    • Extended Temperature 135- and 216-MHz Devices are Available
  • ARM926EJ-S Core
    • Support for 32-Bit and 16-Bit (Thumb Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM® Jazelle® Technology
    • EmbeddedICE-RT™ Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 32K-Byte RAM
    • 8K-Byte ROM
    • Little Endian
  • Video Processing Subsystem
    • Front End Provides:
      • Hardware IPIPE for Real-Time Image Processing
      • Up to 14-bit CCD/CMOS Digital Interface
      • 16-/8-bit Generic YcBcR-4:2 Interface (BT.601)
      • 10-/8-bit CCIR6565/BT655 Interface
      • Up to 75-MHz Pixel Clock
      • Histogram Module
      • Resize Engine
        • Resize Images From 1/16x to 8x
        • Separate Horizontal/Vertical Control
        • Two Simultaneous Output Paths
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • Composite NTSC/PAL video encoder output
      • 8-/16-bit YCC and Up to 18-Bit RGB666 Digital Output
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
      • Digital HDTV (720p/1080i)output for connection to external encoder
  • External Memory Interfaces (EMIFs)
    • DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O)
    • Asynchronous16-/8-bit Wide EMIF (AEMIF)
      • Flash Memory Interfaces
        • NAND (8-/16-bit Wide Data)
        • OneNAND(16-bit Wide Data)
  • Flash Card Interfaces
    • Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
    • SmartMedia
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • USB Port with Integrated 2.0 High-Speed PHY that Supports
    • USB 2.0 Full and High-Speed Device
    • USB 2.0 Low, Full, and High-Speed Host
  • Three 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
  • One 64-Bit Watch Dog Timer
  • Three UARTs (One fast UART with RTS and CTS Flow Control)
  • Three Serial Port Interfaces (SPI) each with two Chip-Selects
  • One Master/Slave Inter-Integrated Circuit (I2C) Bus®
  • Two Audio Serial Port (ASP)
    • I2S and TDM I2S
    • AC97 Audio Codec Interface
    • S/PDIF via Software
    • Standard Voice Codec Interface (AIC12)
    • SPI Protocol (Master Mode Only)
  • Four Pulse Width Modulator (PWM) Outputs
  • Four RTO (Real Time Out) Outputs
  • Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
  • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART
  • Configurable Power-Saving Modes
  • Crystal or External Clock Input (typically 24 MHz or 36 MHz)
  • Flexible PLL Clock Generators
  • Debug Interface Support
    • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
    • ETB™ (Embedded Trace Buffer™) with4K-Bytes Trace Buffer memory
    • Device Revision ID Readable by ARM
  • 337-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch
  • 90nm Process Technology
  • 3.3-V and 1.8-V I/O, 1.3-V Internal
  • Community Resources

Windows is a trademark of Microsoft.
All other trademarks are the property of their respective owners.

  • Highlights
    • High-Performance Digital Media System-On-Chip (DMSoC)
    • Up to 216-MHz ARM926EJ-STM Clock Rate
    • Digital HDTV (720p/1080i) output for connection to external encoder
    • Video Processing Subsystem
      • Hardware IPIPE for Real-Time Image Processing
      • Up to 14-bit CCD/CMOS Digital Interface
      • Histogram Module
      • Resize Image 1/16x to 8x
      • Hardware On-Screen Display
      • Up to 75-MHz Pixel Clock
      • Composite NTSC/PAL video encoder output
    • Peripherals include DDR and mDDR SDRAM, 2 MMC/SD/SDIO and SmartMedia Flash Card Interfaces, USB 2.0, 3 UARTs and 3 SPIs
    • Enhanced Direct-Memory-Access (EDMA)
    • Configurable Power-Saving Modes
    • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART
    • 3.3-V and 1.8-V I/O, 1.3-V Core
    • Debug Interface Support
    • Up to 104 General-Purpose I/O (GPIO) Pins
    • 337-Pin Ball Grid Array at 65 nm Process Technology
  • High-Performance Digital Media System-on-Chip
    • 135-, 216-MHz ARM926EJ-S™ Clock Rate
    • Fully Software-Compatible With ARM™
    • Extended Temperature 135- and 216-MHz Devices are Available
  • ARM926EJ-S Core
    • Support for 32-Bit and 16-Bit (Thumb Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM® Jazelle® Technology
    • EmbeddedICE-RT™ Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 32K-Byte RAM
    • 8K-Byte ROM
    • Little Endian
  • Video Processing Subsystem
    • Front End Provides:
      • Hardware IPIPE for Real-Time Image Processing
      • Up to 14-bit CCD/CMOS Digital Interface
      • 16-/8-bit Generic YcBcR-4:2 Interface (BT.601)
      • 10-/8-bit CCIR6565/BT655 Interface
      • Up to 75-MHz Pixel Clock
      • Histogram Module
      • Resize Engine
        • Resize Images From 1/16x to 8x
        • Separate Horizontal/Vertical Control
        • Two Simultaneous Output Paths
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • Composite NTSC/PAL video encoder output
      • 8-/16-bit YCC and Up to 18-Bit RGB666 Digital Output
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
      • Digital HDTV (720p/1080i)output for connection to external encoder
  • External Memory Interfaces (EMIFs)
    • DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O)
    • Asynchronous16-/8-bit Wide EMIF (AEMIF)
      • Flash Memory Interfaces
        • NAND (8-/16-bit Wide Data)
        • OneNAND(16-bit Wide Data)
  • Flash Card Interfaces
    • Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
    • SmartMedia
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • USB Port with Integrated 2.0 High-Speed PHY that Supports
    • USB 2.0 Full and High-Speed Device
    • USB 2.0 Low, Full, and High-Speed Host
  • Three 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
  • One 64-Bit Watch Dog Timer
  • Three UARTs (One fast UART with RTS and CTS Flow Control)
  • Three Serial Port Interfaces (SPI) each with two Chip-Selects
  • One Master/Slave Inter-Integrated Circuit (I2C) Bus®
  • Two Audio Serial Port (ASP)
    • I2S and TDM I2S
    • AC97 Audio Codec Interface
    • S/PDIF via Software
    • Standard Voice Codec Interface (AIC12)
    • SPI Protocol (Master Mode Only)
  • Four Pulse Width Modulator (PWM) Outputs
  • Four RTO (Real Time Out) Outputs
  • Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
  • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART
  • Configurable Power-Saving Modes
  • Crystal or External Clock Input (typically 24 MHz or 36 MHz)
  • Flexible PLL Clock Generators
  • Debug Interface Support
    • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
    • ETB™ (Embedded Trace Buffer™) with4K-Bytes Trace Buffer memory
    • Device Revision ID Readable by ARM
  • 337-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch
  • 90nm Process Technology
  • 3.3-V and 1.8-V I/O, 1.3-V Internal
  • Community Resources

Windows is a trademark of Microsoft.
All other trademarks are the property of their respective owners.

The DM335 processor is a low-cost, low-power processor providing advanced graphical user interface for display applications that do not require video compression and decompression. Coupled with a video processing subsystem (VPSS) that provides 720p display, the DM335 processor is powered by a 135/216-MHz ARM926EJ-S core so developers can create feature-rich graphical user interfaces allowing customers to interact with their portable, electronic devices such as video-enabled universal remote controls, Internet radio, e-books, video doorbells, and digital telescopes. The new DM335 is packed with the same peripherals as its predecessor, the TMS320DM355 device, including high-speed USB 2.0 on-the-go, external memory interface (EMIF), mobile DDR/DDR2, two SDIO ports, three UART Ports, two Audio Serial Ports, three SPI Ports, and SLC/MCL NAND Flash memory support. These peripherals help customers create DM335 processor-based designs that add video and audio excitement to a wide range of today's static user-interface applications while keeping silicon costs and power consumption low. The new digital media processor is completely scalable with the DM355 processor and Digital Video Evaluation Board (DVEVM), allowing customers to utilize their same code for their new DM335 processor focused designs.

The new DM335 device delivers a sophisticated suite of capabilities allowing for flexible image capture and display. Through its user interface technology, such as a four-level on-screen display, developers are able to create picture-within-picture and video-within-video as well as innovative graphic user interfaces. This is especially important for portable products that require the use of button or touch screen, such as portable karaoke, video surveillance and electronic gaming applications. Additional advanced capture and imaging technologies include support for CCD/CMOS image sensors, resize capability and video stabilization. The 1280-by-960-pixel digital LCD connection runs on a 75-MHz pixel clock and supports TV composite output for increased expandability. This highly integrated device is packaged in a 13 x 13 mm, 337 pin , 0.65 mm pitch BGA package.

The DM335 processor core is an ARM926EJ-S RISC processor. The ARM926EJ-S is a 32-bit processor core that performs 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core incorporates:

  • A coprocessor 15 (CP15) and protection module
  • Data and program Memory Management Units (MMUs) with table look-aside buffers.
  • Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

The DM335 device has a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals:

  • A Video Processing Front-End (VPFE)
  • A Video Processing Back-End (VPBE)

The VPFE port provides an interface for CCD/CMOS imager modules and video decoders. The VPBE provides hardware On Screen Display (OSD) support and composite NTSC/PAL and digital LCD output.

The DM335 peripheral set includes:

  • An inter-integrated circuit (I2C) Bus interface
  • Two audio serial ports (ASP)
  • Three 64-bit general-purpose timers each configurable as two independent 32-bit timers
  • A 64-bit watchdog timer
  • Up to 104-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals
  • Three UARTs with hardware handshaking support on one UART
  • Three serial port Interfaces (SPI)
  • Four pulse width modulator (PWM) peripherals
  • Four real time out (RTO) outputs
  • Two Multi-Media Card / Secure Digital (MMC/SD/SDIO) interfaces
  • Wireless interfaces (Bluetooth, WLAN, WUSB) through SDIO
  • A USB 2.0 full and high-speed device and host interface
  • Two external memory interfaces:
    • An asynchronous external memory interface (AEMIF) for slower memories/peripherals such as NAND and OneNAND,
    • A high speed synchronous memory interface for DDR2/mDDR.

For software development support the DM335 has a complete set of ARM development tools which include: C compilers, assembly optimizers to simplify programming and scheduling, and a Windows™debugger interface for visibility into source code execution.

The DM335 processor is a low-cost, low-power processor providing advanced graphical user interface for display applications that do not require video compression and decompression. Coupled with a video processing subsystem (VPSS) that provides 720p display, the DM335 processor is powered by a 135/216-MHz ARM926EJ-S core so developers can create feature-rich graphical user interfaces allowing customers to interact with their portable, electronic devices such as video-enabled universal remote controls, Internet radio, e-books, video doorbells, and digital telescopes. The new DM335 is packed with the same peripherals as its predecessor, the TMS320DM355 device, including high-speed USB 2.0 on-the-go, external memory interface (EMIF), mobile DDR/DDR2, two SDIO ports, three UART Ports, two Audio Serial Ports, three SPI Ports, and SLC/MCL NAND Flash memory support. These peripherals help customers create DM335 processor-based designs that add video and audio excitement to a wide range of today's static user-interface applications while keeping silicon costs and power consumption low. The new digital media processor is completely scalable with the DM355 processor and Digital Video Evaluation Board (DVEVM), allowing customers to utilize their same code for their new DM335 processor focused designs.

The new DM335 device delivers a sophisticated suite of capabilities allowing for flexible image capture and display. Through its user interface technology, such as a four-level on-screen display, developers are able to create picture-within-picture and video-within-video as well as innovative graphic user interfaces. This is especially important for portable products that require the use of button or touch screen, such as portable karaoke, video surveillance and electronic gaming applications. Additional advanced capture and imaging technologies include support for CCD/CMOS image sensors, resize capability and video stabilization. The 1280-by-960-pixel digital LCD connection runs on a 75-MHz pixel clock and supports TV composite output for increased expandability. This highly integrated device is packaged in a 13 x 13 mm, 337 pin , 0.65 mm pitch BGA package.

The DM335 processor core is an ARM926EJ-S RISC processor. The ARM926EJ-S is a 32-bit processor core that performs 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core incorporates:

  • A coprocessor 15 (CP15) and protection module
  • Data and program Memory Management Units (MMUs) with table look-aside buffers.
  • Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

The DM335 device has a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals:

  • A Video Processing Front-End (VPFE)
  • A Video Processing Back-End (VPBE)

The VPFE port provides an interface for CCD/CMOS imager modules and video decoders. The VPBE provides hardware On Screen Display (OSD) support and composite NTSC/PAL and digital LCD output.

The DM335 peripheral set includes:

  • An inter-integrated circuit (I2C) Bus interface
  • Two audio serial ports (ASP)
  • Three 64-bit general-purpose timers each configurable as two independent 32-bit timers
  • A 64-bit watchdog timer
  • Up to 104-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals
  • Three UARTs with hardware handshaking support on one UART
  • Three serial port Interfaces (SPI)
  • Four pulse width modulator (PWM) peripherals
  • Four real time out (RTO) outputs
  • Two Multi-Media Card / Secure Digital (MMC/SD/SDIO) interfaces
  • Wireless interfaces (Bluetooth, WLAN, WUSB) through SDIO
  • A USB 2.0 full and high-speed device and host interface
  • Two external memory interfaces:
    • An asynchronous external memory interface (AEMIF) for slower memories/peripherals such as NAND and OneNAND,
    • A high speed synchronous memory interface for DDR2/mDDR.

For software development support the DM335 has a complete set of ARM development tools which include: C compilers, assembly optimizers to simplify programming and scheduling, and a Windows™debugger interface for visibility into source code execution.

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No design support from TI available

This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.

技術文件

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類型 標題 日期
* Data sheet TMS320DM335 Digital Media System-on-Chip (DMSoC) datasheet (Rev. C) 2010年 6月 24日
* Errata TMS320DM335 Digital Media System-on-Chip Silicon Erata (Revs 1.1, 1.3 and 1.4) (Rev. B) 2010年 1月 24日
Application note High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 2023年 2月 24日
Application note Powering the TMS320DM335 and TMS320DM355 with the TPS650061 2011年 10月 13日
Application note Migrating From TMS320DM355/335 Silicon Revision 1.1 to 1.3 or 1.4 (Rev. B) 2011年 1月 5日
User guide TMS320DM335 DMSoC Pulse-Width Modulator User's Guide (Rev. A) 2010年 8月 25日
User guide TMS320DM335 DMSoC ARM Subsystem Reference Guide (Rev. A) 2010年 7月 15日
More literature TMS320DM3x DaVinci Video Processors 2010年 4月 11日
Application note Implementing DDR2/mDDR PCB Layout on the TMS320DM335 DMSoC (Rev. D) 2009年 11月 11日
More literature TMS320DM3x Highlights 2009年 3月 3日
More literature Complimentary Analog Devices for the DM335 Digital Media Processor 2009年 2月 17日
User guide TMS320DM335 DMSoC Video Processing Back-End User's Guide (Rev. A) 2008年 10月 24日
More literature DaVinci Technology Overview Brochure (Rev. B) 2008年 9月 27日
Application note Migrating from EDMA v2.0 to EDMA v3.0 TMS320C64X DSP (Rev. A) 2008年 8月 21日
Application note TMS320DM355 DSP Power Reference Design PR742 (Rev. A) 2008年 8月 8日
Application note Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) 2008年 7月 17日
User guide TMS320DM335 DMSoC Asynchronous External Memory Interface(EMIF) 2008年 7月 15日
User guide TMS320DM335 DMSoC Audio Serial Port 2008年 7月 15日
User guide TMS320DM335 DMSoC DDR2/mDDR Memory Controller Reference Guide 2008年 7月 15日
User guide TMS320DM335 DMSoC Enhanced Direct Memory Access (EDMA) Controller User's Guide 2008年 7月 15日
User guide TMS320DM335 DMSoC General-Purpose Input/Output (GPIO) User's Guide 2008年 7月 15日
User guide TMS320DM335 DMSoC Inter-Integrated Circuit (I2C) 2008年 7月 15日
User guide TMS320DM335 DMSoC MMC/SD Reference Guide 2008年 7月 15日
User guide TMS320DM335 DMSoC Peripheral Overview Reference Guide 2008年 7月 15日
User guide TMS320DM335 DMSoC Real Time Out (RTO) User's Guide 2008年 7月 15日
User guide TMS320DM335 DMSoC Serial Peripheral Interface (SPI) 2008年 7月 15日
User guide TMS320DM335 DMSoC Timer/Watchdog Timer User's Guide 2008年 7月 15日
User guide TMS320DM335 DMSoC Universal Asynchronous Receiver/Transmitter (UART) 2008年 7月 15日
User guide TMS320DM335 DMSoC Universal Serial Bus (USB) User's Guide 2008年 7月 15日
User guide TMS320DM335 DMSoC Video Processing Front-End User's Guide 2008年 7月 15日
Application note Building a Small Embedded Linux Kernel Example (Rev. A) 2008年 5月 27日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

偵錯探測器

TMDSEMU200-U — XDS200 USB 偵錯探測器

XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器 (模擬器)。與低成本 XDS110 和高效能 XDS560v2 相比,XDS200 是兼具低成本與優異效能的完美平衡,可在單一 pod 中支援各種標準 (IEEE1149.1、IEEE1149.7、SWD)。所有 XDS 偵錯探測器均支援具嵌入式追踪緩衝區 (ETB) 的 Arm® 與 DSP 處理器中的核心和系統追蹤功能。透過針腳進行核心追蹤則需要 XDS560v2 PRO TRACE

XDS200 透過 TI 20 針腳連接器 (配備適用 TI 14 針腳、Arm Cortex® 10 針腳和 Arm 20 針腳的多重轉接器) (...)

TI.com 無法提供
偵錯探測器

TMDSEMU560V2STM-U — XDS560v2 System Trace USB 偵錯探測器

XDS560v2 是 XDS560™ 偵錯探測器系列的最高性能表現,支援傳統 JTAG 標準 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。請注意,序列線偵錯 (SWD) 不受支援。

所有 XDS 偵錯探測器均支援所有具有嵌入式追踪緩衝區 (ETB) 的 ARM 和 DSP 處理器中的核心和系統追蹤功能。對於針腳追蹤則需要 XDS560v2 PRO TRACE

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板,並透過 USB2.0 高速 (480Mbps) (...)

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偵錯探測器

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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軟體開發套件 (SDK)

LINUXDVSDK-DV — Linux 數位視訊軟體開發套件 (DVSDK) v2x/v3x - DaVinci 數位媒體處理器

Effective Oct 2010 - Linux DVSDK v4 has been released. For DaVinci™ devices not listed above, search TI.com for your device part number; This product page will have a link to your current DVSDK.

The Linux™ Digital Video Software Development Kits (DVSDKs) enable DaVinci system integrators to (...)

應用軟體及架構

TMDMFP — 多媒體框架產品 (MFP) - 轉碼器引擎、框架元件和 XDAIS

Multimedia Framework Products (MFP)

A major advantage of programmable signal processors over fixed-function devices is their ability to accelerate multiple multimedia functions and provide flexible environments to enable user customization. However, sharing scarce embedded hardware resources between (...)

使用指南: PDF
模擬型號

DM335 ZCE BSDL Model

SPRM318.ZIP (8 KB) - BSDL Model
模擬型號

DM335 ZCE IBIS Model (Rev. A)

SPRM317A.ZIP (234 KB) - IBIS Model
參考設計

PR2047 — 用 TPS650061 給 TMS320DM335 和 TMS320DM355 供電

Low cost integrated power solution for TI - DM335/355 processors
Test report: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
NFBGA (ZCE) 337 Ultra Librarian

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

支援與培訓

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