SLVAF64A July   2021  – November 2022 TPS62800 , TPS62801 , TPS62802 , TPS62806 , TPS62807 , TPS62808 , TPS62864 , TPS62865 , TPS62866 , TPS62867 , TPS62868 , TPS62869 , TPSM82810 , TPSM82813 , TPSM82816 , TPSM82864A , TPSM82866A , TPSM82866C , TPSM8287A06 , TPSM8287A10 , TPSM8287A15

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Standard Device Operation: Resistance Measurement and Digital Input
  5. 3TPS62864/6/8/9: VSET/VID Pin
  6. 4TPS62800/1/2/6/7/8: VSEL/MODE Pin
  7. 5TPS62865/7 and TPSM82864/6A: VSET/MODE Pin
  8. 6Summary
  9. 7Revision History

5 TPS62865/7 and TPSM82864/6A: VSET/MODE Pin

TPS62865/7 and TPSM82864/6A ICs have the VSET/MODE pin, that is functionally equivalent to the previously described VSEL/MODE pin (TPS62865/TPS62867 2.4-V to 5.5-V Input, 4-A and 6-A Synchronous Step-Down Converter in 1.5-mm × 2.5-mm QFN Package and TPSM82864A/TPSM82866A 2.4-V to 5.5-V Input, 4-A/6-A Step-Down Power Module with an Integrated Inductor in a 3.5-mm × 4.0-mm Thin Overmolded QFN Package data sheets).

Figure 5-1 Typical Application Schematics TPS62865/7 – Fixed Output Voltage
Figure 5-2 Typical Application Schematic TPSM82864/6A - Fixed Output Voltage

The main difference with respect to the previous devices is that here an additional pin (FB) is present. The FB pin can to be used to properly select the output voltage with the classical feedback divider when VSET/MODE pin is connected to a logic high or logic low level.

Figure 5-3 Typical Application Schematics TPS62865/7 – Forced PWM Operation
Figure 5-4 Typical Application Schematics TPSM82864/6A – Forced PWM Operation

With these devices, the simplest solution to select the forced-PWM mode is to connect the VSET/MODE pin to high potential and then use the FB divider to properly select the output voltage as shown in Figure 5-3 and Figure 5-4.

The main advantage of the last configuration is the possibility to decouple VSET and MODE functionality, giving the possibility to the designer to effectively select the mode of operation without limiting the output voltage level selection. With this solution, no additional components are required and no parasitics are introduced, leading to a simple and straightforward design process.