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CDCLVD2102

ACTIVE

Low jitter, dual 1:2 universal-to-LVDS buffer

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Data sheet

CDCLVD2102

ACTIVE
Data sheet Order now

Product details

Function Differential Additive RMS jitter (typ) (fs) 171 Output frequency (max) (MHz) 800 Number of outputs 4 Output supply voltage (V) 2.5 Core supply voltage (V) 2.5 Output skew (ps) 15 Features Dual 1:2 fanout, Output enable control, Universal inputs Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVDS Input type LVCMOS, LVDS, LVPECL
Function Differential Additive RMS jitter (typ) (fs) 171 Output frequency (max) (MHz) 800 Number of outputs 4 Output supply voltage (V) 2.5 Core supply voltage (V) 2.5 Output skew (ps) 15 Features Dual 1:2 fanout, Output enable control, Universal inputs Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVDS Input type LVCMOS, LVDS, LVPECL
VQFN (RGT) 16 9 mm² 3 x 3
  • Dual 1:2 Differential Buffer
  • Low Additive Jitter <300 fs RMS in 10-kHz to 20-MHz
  • Low Within Bank Output Skew of 15 ps (Max)
  • Universal Inputs Accept LVDS, LVPECL, LVCMOS
  • One Input Dedicated for Two Outputs
  • Total of 4 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
  • Clock Frequency up to 800 MHz
  • 2.375–2.625V Device Power Supply
  • LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs
  • Industrial Temperature Range –40°C to 85°C
  • Packaged in 3mm × 3mm 16-Pin QFN (RGT)
  • ESD Protection Exceeds 3 kV HBM, 1 kV CDM
  • APPLICATIONS
    • Telecommunications/Networking
    • Medical Imaging
    • Test and Measurement Equipment
    • Wireless Communications
    • General Purpose Clocking
  • Dual 1:2 Differential Buffer
  • Low Additive Jitter <300 fs RMS in 10-kHz to 20-MHz
  • Low Within Bank Output Skew of 15 ps (Max)
  • Universal Inputs Accept LVDS, LVPECL, LVCMOS
  • One Input Dedicated for Two Outputs
  • Total of 4 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
  • Clock Frequency up to 800 MHz
  • 2.375–2.625V Device Power Supply
  • LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs
  • Industrial Temperature Range –40°C to 85°C
  • Packaged in 3mm × 3mm 16-Pin QFN (RGT)
  • ESD Protection Exceeds 3 kV HBM, 1 kV CDM
  • APPLICATIONS
    • Telecommunications/Networking
    • Medical Imaging
    • Test and Measurement Equipment
    • Wireless Communications
    • General Purpose Clocking

The CDCLVD2102 clock buffer distributes two clock inputs (IN0, IN1) to a total of 4 pairs of differential LVDS clock outputs (OUT0, OUT3). Each buffer block consists of one input and 2 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD2102 is specifically designed for driving 50- transmission lines. If driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.

Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical "0"), if switched to a logical "1", one buffer with two outputs is disabled and another buffer with two outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2102 is packaged in small 16-pin, 3-mm × 3-mm QFN package.

The CDCLVD2102 clock buffer distributes two clock inputs (IN0, IN1) to a total of 4 pairs of differential LVDS clock outputs (OUT0, OUT3). Each buffer block consists of one input and 2 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD2102 is specifically designed for driving 50- transmission lines. If driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.

Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical "0"), if switched to a logical "1", one buffer with two outputs is disabled and another buffer with two outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2102 is packaged in small 16-pin, 3-mm × 3-mm QFN package.
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LMK00301 ACTIVE 3-GHz, 10-output differential fanout buffer / level translator Ultra low additive jitter,1:10 universal differential buffer that can support LVDS
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Technical documentation

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Type Title Date
* Data sheet Dual 1:2 Low Additive Jitter LVDS Buffer datasheet (Rev. A) 15 Jun 2010
User guide Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board 14 Jun 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

CDCLVD2102EVM — CDCLVD2102 Evaluation Module

The CDCLVD1204/CDCLVD2102 are high-performance, low-additive jitter clock buffers. They have twouniversal input buffers that support single-ended or differential clock inputs and are selectable through a control pin (for CDCLVD1204 only). The devices also feature on-chip bias generators that can (...)
User guide: PDF
Not available on TI.com
Simulation model

CDCLVD2102 IBIS Model (Rev. B)

SLLM093B.ZIP (14 KB) - IBIS Model
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Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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Design tool

PLLATINUMSIM-SW — PLLatinum Sim Tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Supported products & hardware

Supported products & hardware

Products
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Clock generators
LMK03318 — Ultra-low jitter clock generator family with single PLL LMK03328 — Ultra-low jitter clock generator family with two independent PLLs LMK03806 — Ultra-low jitter clock generator with 14 outputs
Clock jitter cleaners
LMK04208 — Ultra low-noise clock jitter cleaner with 6 programmable outputs LMK04368-EP — Enhanced product ultra-low-noise 3.2-GHz JESD204C jitter cleaner LMK04714-Q1 — Automotive, ultra low-noise 3.2-GHz, JESD204B and JESD204C dual-loop clock jitter cleaner LMK04803 — Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 1.9-GHz VCO LMK04805 — Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 2.2-GHz VCO LMK04806 — Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 2.5-GHz VCO LMK04808 — Low-noise clock jitter cleaner with dual loop PLLs and integrated 2.9-GHz VCO LMK04816 — Three input low-noise clock jitter cleaner with dual loop PLLs LMK04821 — Ultra low jitter synthesizer and jitter cleaner with JESD204B support LMK04826 — Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 1840 to1970-MHz VCO0 LMK04828 — Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0. LMK04828-EP — Ultra low-noise JESD204B compliant clock jitter cleaner with temperature range -55 to 105c LMK04832 — Ultra-low-noise, 3.2-GHz, 15-output, JESD204B clock jitter cleaner with dual loop LMK04832-SEP — Radiation-tolerant, 30-krad, ultra-low-noise, 3.2-GHz 15-output JESD204C clock jitter cleaner LMK04832-SP — Radiation-hardened-assured (RHA), ultra-low-noise, 3.2-GHz, 15-output clock jitter cleaner LMK04906 — Ultra low noise clock jitter cleaner/multiplier with 6 programmable outputs
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RF PLLs & synthesizers
LMX1204 — 12.8-GHz RF buffer, multiplier and divider with JESD204B/C SYSREF support and phase synchronization LMX1214 — 1:5 18GHz RF buffer and divider with auxiliary clock LMX1906-SP — Radiation-hardness-assured (RHA) 15GHz buffer, multiplier and divider with SYSREF and FPGA clock LMX2430 — 3.0-GHz/0.8-GHz PLLatinum dual high frequency synthesizer for RF personal communications LMX2433 — 3.6-GHz/1.7-GHz PLLatinum dual high frequency synthesizer for RF personal communications LMX2434 — 5.0-GHz/2.5-GHz PLLatinum low power dual frequency synthesizer for RF personal communications LMX2470 — 2.6-GHz delta-sigma fractional-N PLL with 800-MHz integer-N PLL LMX2485 — 500-MHz to 3-GHz delta-sigma low power dual PLL for RF personal communications LMX2485E — 50-MHz to 3-GHz delta-sigma low power dual PLL for RF personal communications LMX2485Q-Q1 — 500MHz to 3GHz automotive delta-sigma low power dual PLL LMX2486 — 1-GHz to 4.5-GHz delta-sigma low power dual PLL for RF personal communications LMX2487 — 1 to 6-GHz delta-sigma low power dual PLLatinum frequency synthesizer with 3.0-GHz integer PLL LMX2487E — 3-GHz to 7.5-GHz delta-sigma low power dual PLL for RF personal communications LMX2491 — 6.4-GHz low noise fractional-N PLL with ramp/chirp generation LMX2492 — 500MHz to 14GHz wideband, low noise fractional-N PLL with ramp/chirp generation LMX2492-Q1 — Automotive grade 500-MHz to 14-GHz wideband, low noise fractional-N PLL with ramp/chirp generation LMX2531 — High performance frequency synthesizer system with integrated VCO LMX2541 — Ultra-low noise PLLatinum frequency synthesizer with integrated VCO LMX2571 — 1.34-GHz, low-power, extreme-temperature RF synthesizer with frequency-shift keying (FSK) modulation LMX2571-EP — Enhanced-product, 1.34-GHz, low-power, extreme-temperature RF synthesizer with FSK modulation LMX2572 — 6.4-GHz low-power wideband RF synthesizer LMX2572LP — 2-GHz low power wideband RF synthesizer with FSK modulation LMX2581 — 3.76-GHz wideband frequency synthesizer with integrated VCO LMX2581E — 3.8-GHz wideband frequency synthesizer with integrated VCO LMX2582 — 5.5-GHz high performance, wideband PLLatinum RF synthesizer LMX2592 — 9.8-GHz wideband frequency synthesizer with integrated VCO LMX2594 — 15-GHz wideband PLLatinum™ RF synthesizer with phase synchronization and JESD204B support LMX2595 — 20-GHz wideband RF synthesizer with phase synchronization & JESD204B support LMX2615-SP — Space grade 40-MHz to 15-GHz wideband synthesizer with phase synchronization and JESD204B support LMX2694-EP — Enhanced product 15-GHz RF synthesizer with phase synchronization TRF3765 — 300M-4800MHz Low Noise Integer-N/Fractional-N PLL with Integrated VCO and up to 8 Outputs
IQ demodulators
LMX8410L — High-Performance Mixer With Integrated Synthesizer
Hardware development
Evaluation board
LMK04832EVM — LMK04832 JESD204B Clock Jitter Cleaner/Clock Generator/Distribution Evaluation Module LMX2571EPEVM — LMX2571-EP evaluation module for 1.34-GHz, low-power, extreme-temperature RF synthesizer LMX2594PSEVM — LMX2594 evaluation module for 15-GHz RF synthesizer with multiple-device phase synchronization XMICR-3P-LMX2492 — LMX2492 X-MWblock evaluation modules XMICR-3P-LMX2572 — LMX2572 X-MWblock evaluation modules XMICR-3P-LMX2592 — LMX2592 X-MWblock evaluation modules XMICR-3P-LMX2594 — LMX2594 X-MWblock evaluation modules XMICR-3P-LMX2595 — LMX2595 X-MWblock evaluation modules
Software
Application software & framework
TICSPRO-SW — Texas Instruments Clocks and Synthesizers (TICS) Pro Software
IDE, configuration, compiler or debugger
CODELOADER — CodeLoader Software for device register programming
Support software
LMX9830-SW — LMX9830 Application Notes, Software, and Tools LMX9838-SW — LMX9838 Application Notes, Software, and Tools
Download options
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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