The DS25BR120 is a single channel 3.125 Gbps LVDS buffer optimized for high-speed signal
transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. Fully
differential signal paths ensure exceptional signal integrity and noise immunity.
The DS25BR120 features four levels of pre-emphasis (PE) for use as an optimized driver
device. Other LVDS devices with similar IO characteristics include the following products. The
DS25BR110 features four levels of equalization for use as an optimized receiver device, while the
DS25BR100 features both pre-emphasis and equalization for use as an optimized repeater device. The
DS25BR150 is a buffer/repeater with the lowest power consumption and does not feature transmit
pre-emphasis nor receive equalization.
Wide input common mode range allows the receiver to accept signals with LVDS, CML and
LVPECL levels; the output levels are LVDS. A very small package footprint requires minimal space on
the board while the flow-through pinout allows easy board layout. The differential inputs and
outputs are internally terminated with a 100Ω resistor to lower device input and output return
losses, reduce component count and further minimize board space.
The DS25BR120 is a single channel 3.125 Gbps LVDS buffer optimized for high-speed signal
transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. Fully
differential signal paths ensure exceptional signal integrity and noise immunity.
The DS25BR120 features four levels of pre-emphasis (PE) for use as an optimized driver
device. Other LVDS devices with similar IO characteristics include the following products. The
DS25BR110 features four levels of equalization for use as an optimized receiver device, while the
DS25BR100 features both pre-emphasis and equalization for use as an optimized repeater device. The
DS25BR150 is a buffer/repeater with the lowest power consumption and does not feature transmit
pre-emphasis nor receive equalization.
Wide input common mode range allows the receiver to accept signals with LVDS, CML and
LVPECL levels; the output levels are LVDS. A very small package footprint requires minimal space on
the board while the flow-through pinout allows easy board layout. The differential inputs and
outputs are internally terminated with a 100Ω resistor to lower device input and output return
losses, reduce component count and further minimize board space.