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CDCLVC1310

ACTIVE

Universal input, 10-output low impedance LVCMOS buffer

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Data sheet

CDCLVC1310

ACTIVE
Data sheet Order now

Product details

Function Single-ended Additive RMS jitter (typ) (fs) 25 Output frequency (max) (MHz) 200 Number of outputs 10 Output supply voltage (V) 1.5, 1.8, 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 50 Features 1:10 fanout, Level translation Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVCMOS Input type HCSL, LVCMOS, LVDS, LVPECL, SSTL, XTAL
Function Single-ended Additive RMS jitter (typ) (fs) 25 Output frequency (max) (MHz) 200 Number of outputs 10 Output supply voltage (V) 1.5, 1.8, 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 50 Features 1:10 fanout, Level translation Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVCMOS Input type HCSL, LVCMOS, LVDS, LVPECL, SSTL, XTAL
VQFN (RHB) 32 25 mm² 5 x 5
  • High-Performance Crystal Buffer With Ultralow Noise
    Floor of –169 dBc/Hz
  • Additive Phase Noise/Jitter Performance Is
    25 fsRMS (Typ.)
  • Level Translation With 3.3-V or 2.5-V Core and
    3.3-V, 2.5-V, 1.8-V, or 1.5-V Output Supply
  • Device inputs consist of primary, secondary,
    and crystal inputs, and manually selectable
    (through pins) using the input MUX. The primary
    and secondary inputs can accept LVPECL, LVDS,
    HCSL, SSTL or LVCMOS signals and crystal input.
    • Crystal Frequencies Supported Are From
      8 MHz to 50 MHz
    • Differential and Single-Ended Input Frequencies
      Supported Are up to 200 MHz
  • 10 Single-Ended LVCMOS Outputs. The outputs can
    operate at 1.5-V, 1.8-V, 2.5-V or 3.3-V
    Power-Supply Voltage.
    • LVCMOS Outputs Operate up to 200 MHz
    • Output Skew Is 30 ps (Typical)
    • Total Propagation Delay Is 2 ns (Typical)
    • Synchronous and Glitch-Free Output Enable Is
      Available
  • Offered in QFN-32 5-mm × 5-mm Package With
    Industrial Temperature Range of –40°C to 85°C
  • Can Overdrive Crystal Input With LVCMOS Signal up to 50 MHz
  • High-Performance Crystal Buffer With Ultralow Noise
    Floor of –169 dBc/Hz
  • Additive Phase Noise/Jitter Performance Is
    25 fsRMS (Typ.)
  • Level Translation With 3.3-V or 2.5-V Core and
    3.3-V, 2.5-V, 1.8-V, or 1.5-V Output Supply
  • Device inputs consist of primary, secondary,
    and crystal inputs, and manually selectable
    (through pins) using the input MUX. The primary
    and secondary inputs can accept LVPECL, LVDS,
    HCSL, SSTL or LVCMOS signals and crystal input.
    • Crystal Frequencies Supported Are From
      8 MHz to 50 MHz
    • Differential and Single-Ended Input Frequencies
      Supported Are up to 200 MHz
  • 10 Single-Ended LVCMOS Outputs. The outputs can
    operate at 1.5-V, 1.8-V, 2.5-V or 3.3-V
    Power-Supply Voltage.
    • LVCMOS Outputs Operate up to 200 MHz
    • Output Skew Is 30 ps (Typical)
    • Total Propagation Delay Is 2 ns (Typical)
    • Synchronous and Glitch-Free Output Enable Is
      Available
  • Offered in QFN-32 5-mm × 5-mm Package With
    Industrial Temperature Range of –40°C to 85°C
  • Can Overdrive Crystal Input With LVCMOS Signal up to 50 MHz

The CDCLVC1310 is a highly versatile, low-jitter, low-power clock fanout buffer which can distribute to ten low-jitter LVCMOS clock outputs from one of three inputs, whose primary and secondary inputs can feature differential or single-ended signals and crystal input. Such a buffer is good for use in a variety of mobile and wired infrastructure, data communication, computing, low-power medical imaging, and portable test and measurement applications. When the input is an illegal level, the output is at a defined state. One can set the core to 2.5 V or 3.3 V, and output to 1.5 V, 1.8 V, 2.5 V or 3.3 V. Pin programming easily configures the CDCLVC1310. The overall additive jitter performance is 25 fsRMS (typical). The CDCLVC1310 comes in a small 32-pin 5-mm × 5-mm QFN package.

The CDCLVC1310 is a highly versatile, low-jitter, low-power clock fanout buffer which can distribute to ten low-jitter LVCMOS clock outputs from one of three inputs, whose primary and secondary inputs can feature differential or single-ended signals and crystal input. Such a buffer is good for use in a variety of mobile and wired infrastructure, data communication, computing, low-power medical imaging, and portable test and measurement applications. When the input is an illegal level, the output is at a defined state. One can set the core to 2.5 V or 3.3 V, and output to 1.5 V, 1.8 V, 2.5 V or 3.3 V. Pin programming easily configures the CDCLVC1310. The overall additive jitter performance is 25 fsRMS (typical). The CDCLVC1310 comes in a small 32-pin 5-mm × 5-mm QFN package.
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Type Title Date
* Data sheet Ten-Output Low-Jitter Low-Power Clock Buffer and Level Translator datasheet (Rev. E) 06 Jan 2014
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 30 Apr 2024
Application note Crystal Oscillator Performance of the CDCLVC1310 09 Aug 2012
Application note Phase Noise Performance of CDCLVC1310 26 Jan 2012
User guide 10-Output Low Jitter Low Power Differential to LVCMOS Clock Buffer - Evaluation 29 Nov 2011

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