Startseite Logik- & Spannungsumsetzung Flipflops, Latches & Register Schieberegister
Startseite
Logik- & Spannungsumsetzung
Flipflops, Latches & Register
Schieberegister

CD54HC194

AKTIV

Bidirektionales Universal-Schieberegister für Highspeed-CMOS-Logik, 4 Bit

Jetzt bestellen
Datenblatt

CD54HC194

AKTIV
Datenblatt Jetzt bestellen

Produktdetails

Configuration Universal Bits (#) 4 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 60 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
Configuration Universal Bits (#) 4 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 60 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92
  • Four Operating Modes
    • Shift Right, Shift Left, Hold and Reset
  • Synchronous Parallel or Serial Operation
  • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25°C
  • Asynchronous Master Reset
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH
  • Four Operating Modes
    • Shift Right, Shift Left, Hold and Reset
  • Synchronous Parallel or Serial Operation
  • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25°C
  • Asynchronous Master Reset
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

The ’HC194 and CD74HCT194 are 4-bit shift registers with Asynchronous Master Reset (MR)\. In the parallel mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock input (CP). During parallel loading serial data flow is inhibited. Shift left and shift right are accomplished synchronously on the positive clock edge with serial data entered at the shift left (DSL) serial input for the shift right mode, and at the shift right (DSR) serial input for the shift left mode. Clearing the register is accomplished by a Low applied to the Master Reset (MR)\ pin.

The ’HC194 and CD74HCT194 are 4-bit shift registers with Asynchronous Master Reset (MR)\. In the parallel mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock input (CP). During parallel loading serial data flow is inhibited. Shift left and shift right are accomplished synchronously on the positive clock edge with serial data entered at the shift left (DSL) serial input for the shift right mode, and at the shift right (DSR) serial input for the shift left mode. Clearing the register is accomplished by a Low applied to the Master Reset (MR)\ pin.
filter Andere Schieberegister suchen
Herunterladen Video mit Transkript ansehen Video

Ähnliche Produkte, die für Sie interessant sein könnten

open-in-new Alternativen vergleichen
Ähnliche Funktionalität wie verglichener Baustein
SN74HC165B-EP AKTIV Verbessertes Produkt – Ach-Bit- Parallellast-Schieberegister Voltage range (2V to 6V), average drive strength (8mA), average propagation delay (20ns)

Technische Dokumentation

star =Von TI ausgewählte Top-Empfehlungen für dieses Produkt
Keine Ergebnisse gefunden. Bitte geben Sie einen anderen Begriff ein und versuchen Sie es erneut.
Alle anzeigen 16
Typ Titel Datum
* Data sheet CD54HC194, CD74HC194, CD74HCT194 datasheet (Rev. G) 01 Mai 2006
* SMD CD54HC194 SMD 5962-86826 21 Jun 2016
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dez 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Okt 1996
Application note Live Insertion 01 Okt 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 Mai 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
CDIP (J) 16 Ultra Librarian
Es gelten die allgemeinen Geschäftsbedingungen von TI für Evaluierungsartikel.

Bestellen & Qualität

Beinhaltete Information:
  • RoHS
  • REACH
  • Bausteinkennzeichnung
  • Blei-Finish/Ball-Material
  • MSL-Rating / Spitzenrückfluss
  • MTBF-/FIT-Schätzungen
  • Materialinhalt
  • Qualifikationszusammenfassung
  • Kontinuierliches Zuverlässigkeitsmonitoring
Beinhaltete Information:
  • Werksstandort
  • Montagestandort

Support und Schulungen

TI E2E™-Foren mit technischem Support von TI-Ingenieuren

Alle Forenthemen auf Englisch anzeigen

Inhalte werden ohne Gewähr von TI und der Community bereitgestellt. Sie stellen keine Spezifikationen von TI dar. Siehe Nutzungsbedingungen.

Bei Fragen zu den Themen Qualität, Gehäuse oder Bestellung von TI-Produkten siehe TI-Support. ​​​​​​​​​​​​​​

Videos