CD54HC563

Name: CD54HC563
Brand: TI
SKU: CD54HC563
Price: 20.86 USD

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Achtfacher invertierender transparenter High-Speed-CMOS-Logik-Latch mit Tri-State-Ausgängen

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Datenblatt

document-pdfAcrobat CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563 datasheet (Rev. C) (Englisch)

CD54HC563

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Datenblatt

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Produktdetails

Number of channels

8

Technology family

HC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

28

IOL (max) (mA)

7.8

IOH (max) (mA)

-7.8

Supply current (max) (µA)

160

Features

Balanced outputs, Flow-through pinout, High speed (tpd 10-50ns), Inverting output, Positive input clamp diode

Operating temperature range (°C)

-55 to 125

Rating

Military

Number of channels

8

Technology family

HC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

28

IOL (max) (mA)

7.8

IOH (max) (mA)

-7.8

Supply current (max) (µA)

160

Features

Balanced outputs, Flow-through pinout, High speed (tpd 10-50ns), Inverting output, Positive input clamp diode

Operating temperature range (°C)

-55 to 125

Rating

Military

CDIP (J)

20

167.464 mm² 24.2 x 6.92

Common Latch-Enable Control
Common Three-State Output Enable Control
Buffered Inputs
Three-State Outputs
Bus Line Driving Capacity
Typical Propagation Delay = 13ns at V_CC = 5V, C_L = 15pF, T_A = 25°C (Data to Output)
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH

Common Latch-Enable Control
Common Three-State Output Enable Control
Buffered Inputs
Three-State Outputs
Bus Line Driving Capacity
Typical Propagation Delay = 13ns at V_CC = 5V, C_L = 15pF, T_A = 25°C (Data to Output)
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH

The ’HC533, ’HCT533, ’HC563, and CD74HCT563 are high speed Octal Transparent Latches manufactured with silicon gate CMOS technology. They possess the low power con-sumption of standard CMOS integrated circuits, as well as the ability to drive 15 LSTTL devices.

The outputs are transparent to the inputs when the latch enable (LE\) is high. When the latch enable (LE\) goes low the data is latched. The output enable (OE\) controls the three-state outputs. When the output enable (OE\) is high the outputs are in the high impedance state. The latch operation is independent of the state of the output enable.

The ’HC533 and ’HCT533 are identical in function to the ’HC563 and CD74HCT563 but have different pinouts. The ’HC533 and ’HCT533 are similar to the ’HC373 and ’HCT373; the latter are non-inverting types.

The ’HC533, ’HCT533, ’HC563, and CD74HCT563 are high speed Octal Transparent Latches manufactured with silicon gate CMOS technology. They possess the low power con-sumption of standard CMOS integrated circuits, as well as the ability to drive 15 LSTTL devices.

The outputs are transparent to the inputs when the latch enable (LE\) is high. When the latch enable (LE\) goes low the data is latched. The output enable (OE\) controls the three-state outputs. When the output enable (OE\) is high the outputs are in the high impedance state. The latch operation is independent of the state of the output enable.

The ’HC533 and ’HCT533 are identical in function to the ’HC563 and CD74HCT563 but have different pinouts. The ’HC533 and ’HCT533 are similar to the ’HC373 and ’HCT373; the latter are non-inverting types.

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	Typ	Titel		Datum
*	Data sheet	CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563 datasheet (Rev. C)		20 Jun 2003
*	SMD	CD54HC563 SMD 5962-86062		21 Jun 2016
	Application note	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	15 Dez 2022
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		26 Jul 2021
	Selection guide	Logic Guide (Rev. AB)		12 Jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		02 Dez 2015
	User guide	LOGIC Pocket Data Book (Rev. B)		16 Jan 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 Jul 2004
	User guide	Signal Switch Data Book (Rev. A)		14 Nov 2003
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		29 Aug 2002
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)		01 Jun 1997
	Application note	Designing With Logic (Rev. C)		01 Jun 1997
	Application note	Input and Output Characteristics of Digital Integrated Circuits		01 Okt 1996
	Application note	Live Insertion		01 Okt 1996
	Application note	SN54/74HCT CMOS Logic Family Applications and Restrictions		01 Mai 1996
	Application note	Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc		01 Apr 1996

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CD54HC563

Achtfacher invertierender transparenter High-Speed-CMOS-Logik-Latch mit Tri-State-Ausgängen

CD54HC563

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