CD74ACT74-Q1

Name: CD74ACT74-Q1
Brand: TI
SKU: CD74ACT74-Q1
Price: 0.319 USD

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Zweifach-Flipflops (Typ D) mit positiver Flankensteuerung, Auto-Produktkatalog, mit Set und Reset

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Datenblatt

document-pdfAcrobat Dual Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset datasheet (Rev. A) (Englisch)

CD74ACT74-Q1

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Datenblatt

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Produktdetails

Number of channels

2

Technology family

ACT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

85

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

80

Features

Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Number of channels

2

Technology family

ACT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

85

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

80

Features

Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 125

Rating

Automotive

SOIC (D)

14

51.9 mm² 8.65 x 6

Qualified for Automotive Applications
Inputs Are TTL-Voltage Compatible
Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
Balanced Propagation Delays
±24-mA Output Drive Current
- Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and Circuit Design

Qualified for Automotive Applications
Inputs Are TTL-Voltage Compatible
Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
Balanced Propagation Delays
±24-mA Output Drive Current
- Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and Circuit Design

The CD74ACT74 dual positive-edge-triggered device is a D-type flip-flop.

A low level at the preset (PRE) or (CLR) clear inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

The CD74ACT74 dual positive-edge-triggered device is a D-type flip-flop.

A low level at the preset (PRE) or (CLR) clear inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

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	Typ	Titel		Datum
*	Data sheet	Dual Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset datasheet (Rev. A)		29 Jan 2008

CD74ACT74-Q1

Zweifach-Flipflops (Typ D) mit positiver Flankensteuerung, Auto-Produktkatalog, mit Set und Reset

CD74ACT74-Q1

Produktdetails

Technische Dokumentation

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