CD74HC4015

Name: CD74HC4015
Brand: TI
SKU: CD74HC4015
Price: 0.657 USD

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Datenblatt

document-pdfAcrobat CD54HC4015, CD74HC4015 datasheet (Rev. C) (Englisch)

CD74HC4015

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Datenblatt

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Produktdetails

Configuration

Serial-in, Parallel-out

Bits (#)

4

Technology family

HC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (MHz)

60

IOL (max) (mA)

5.2

IOH (max) (mA)

-5.2

Supply current (max) (µA)

160

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-55 to 125

Rating

Catalog

Configuration

Serial-in, Parallel-out

Bits (#)

4

Technology family

HC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (MHz)

60

IOL (max) (mA)

5.2

IOH (max) (mA)

-5.2

Supply current (max) (µA)

160

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-55 to 125

Rating

Catalog

PDIP (N)

16

181.42 mm² 19.3 x 9.4

SOIC (D)

16

59.4 mm² 9.9 x 6

Maximum Frequency, Typically 60MHz C_L = 15pF, V_CC = 5V, T_A = 25°C
Positive-Edge Clocking
Overriding Reset
Buffered Inputs and Outputs
Fanout (Over Temperature Range)
- Standard Outputs . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . –55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V

Maximum Frequency, Typically 60MHz C_L = 15pF, V_CC = 5V, T_A = 25°C
Positive-Edge Clocking
Overriding Reset
Buffered Inputs and Outputs
Fanout (Over Temperature Range)
- Standard Outputs . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . –55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V

The ’HC4015 consists of two identical, independent, 4-stage serial-input/parallel-output registers. Each register has independent Clock (CP) and Reset (MR) inputs as well as a single serial Data input. "Q" outputs are available from each of the four stages on both registers. All register stages are D-type, master-slave flip-flops. The logic level present at the Data input is transferred into the first register stage and shifted over one stage at each positive- going clock transition. Resetting of all stages is accomplished by a high level on the reset line.

The device can drive up to 10 low power Schottky equivalent loads. The ’HC4015 is an enhanced version of equivalent CMOS types.

The ’HC4015 consists of two identical, independent, 4-stage serial-input/parallel-output registers. Each register has independent Clock (CP) and Reset (MR) inputs as well as a single serial Data input. "Q" outputs are available from each of the four stages on both registers. All register stages are D-type, master-slave flip-flops. The logic level present at the Data input is transferred into the first register stage and shifted over one stage at each positive- going clock transition. Resetting of all stages is accomplished by a high level on the reset line.

The device can drive up to 10 low power Schottky equivalent loads. The ’HC4015 is an enhanced version of equivalent CMOS types.

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	Typ	Titel		Datum
*	Data sheet	CD54HC4015, CD74HC4015 datasheet (Rev. C)		21 Mai 2003
	Application note	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	15 Dez 2022
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		26 Jul 2021
	Selection guide	Logic Guide (Rev. AB)		12 Jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		02 Dez 2015
	User guide	LOGIC Pocket Data Book (Rev. B)		16 Jan 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 Jul 2004
	User guide	Signal Switch Data Book (Rev. A)		14 Nov 2003
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		29 Aug 2002
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)		01 Jun 1997
	Application note	Designing With Logic (Rev. C)		01 Jun 1997
	Application note	Input and Output Characteristics of Digital Integrated Circuits		01 Okt 1996
	Application note	Live Insertion		01 Okt 1996
	Application note	SN54/74HCT CMOS Logic Family Applications and Restrictions		01 Mai 1996
	Application note	Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc		01 Apr 1996

Design und Entwicklung

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14-24-LOGIC-EVM — Generisches Logikprodukt-Evaluierungsmodul für 14-polige bis 24-polige D-, DB-, DGV-, DW-, DYY-, NS-

Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.

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Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
PDIP (N)	16	Ultra Librarian
SOIC (D)	16	Ultra Librarian

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CD74HC4015

4-stufige statische Highspeed-CMOS-Logik-Schieberegister

CD74HC4015

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