CY74FCT2373T

Name: CY74FCT2373T
Brand: TI
SKU: CY74FCT2373T
Price: 0.239 USD

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Transparente Achtfach-Register (Typ D) mit Tri-State-Ausgängen und seriellen Dämpfungswiderständen

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Datenblatt

document-pdfAcrobat 8-Bit Latch With 3-State Outputs datasheet (Rev. B) (Englisch)

CY74FCT2373T

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Number of channels

8

Technology family

FCT

Supply voltage (min) (V)

4.75

Supply voltage (max) (V)

5.25

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (max) (MHz)

70

IOL (max) (mA)

12

IOH (max) (mA)

-12

Supply current (max) (µA)

200

Features

Balanced outputs, Damping resistors, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

8

Technology family

FCT

Supply voltage (min) (V)

4.75

Supply voltage (max) (V)

5.25

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (max) (MHz)

70

IOL (max) (mA)

12

IOH (max) (mA)

-12

Supply current (max) (µA)

200

Features

Balanced outputs, Damping resistors, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

SOIC (DW)

20

131.84 mm² 12.8 x 10.3

Function and Pinout Compatible With the Fastest Bipolar Logic
25- Output Series Resistors Reduce Transmission-Line Reflection Noise
Reduced V_OH (Typically = 3.3 V) Version of Equivalent FCT Functions
Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
I_off Supports Partial-Power-Down Mode Operation
Matched Rise and Fall Times
3-State Outputs
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Fully Compatible With TTL Input and Output Logic Levels
12-mA Output Sink Current
15-mA Output Source Current

Function and Pinout Compatible With the Fastest Bipolar Logic
25- Output Series Resistors Reduce Transmission-Line Reflection Noise
Reduced V_OH (Typically = 3.3 V) Version of Equivalent FCT Functions
Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
I_off Supports Partial-Power-Down Mode Operation
Matched Rise and Fall Times
3-State Outputs
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Fully Compatible With TTL Input and Output Logic Levels
12-mA Output Sink Current
15-mA Output Source Current

The CY74FCT2373T is an 8-bit, high-speed CMOS, TTL-compatible buffered latch with 3-state outputs that is ideal for driving high-capacitance loads, such as memory and address buffers. On-chip 25- termination resistors at the outputs reduce system noise caused by reflections. The CY74FCT2373T can replace the CY74FCT373T to reduce noise in an existing design.

When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The CY74FCT2373T is an 8-bit, high-speed CMOS, TTL-compatible buffered latch with 3-state outputs that is ideal for driving high-capacitance loads, such as memory and address buffers. On-chip 25- termination resistors at the outputs reduce system noise caused by reflections. The CY74FCT2373T can replace the CY74FCT373T to reduce noise in an existing design.

When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Alle anzeigen 9

	Typ	Titel		Datum
*	Data sheet	8-Bit Latch With 3-State Outputs datasheet (Rev. B)		01 Okt 2001
	Application note	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	15 Dez 2022
	Selection guide	Logic Guide (Rev. AB)		12 Jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		02 Dez 2015
	User guide	LOGIC Pocket Data Book (Rev. B)		16 Jan 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 Jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)		22 Jun 2004
	User guide	CYFCT Parameter Measurement Information		02 Apr 2001
	Selection guide	Advanced Bus Interface Logic Selection Guide		09 Jan 2001

Design und Entwicklung

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CY74FCT2373T

Transparente Achtfach-Register (Typ D) mit Tri-State-Ausgängen und seriellen Dämpfungswiderständen

CY74FCT2373T

Produktdetails

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