CY74FCT573T

Name: CY74FCT573T
Brand: TI
SKU: CY74FCT573T
Price: 0.384 USD

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Transparente Achtfach-Latches (Typ D), mit Tri-State-Ausgängen

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Datenblatt

document-pdfAcrobat 8-Bit Latches With 3-State Outputs datasheet (Englisch)

CY74FCT573T

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Number of channels

8

Technology family

FCT

Supply voltage (min) (V)

4.75

Supply voltage (max) (V)

5.25

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (max) (MHz)

70

IOL (max) (mA)

64

IOH (max) (mA)

-32

Supply current (max) (µA)

200

Features

Flow-through pinout, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

8

Technology family

FCT

Supply voltage (min) (V)

4.75

Supply voltage (max) (V)

5.25

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (max) (MHz)

70

IOL (max) (mA)

64

IOH (max) (mA)

-32

Supply current (max) (µA)

200

Features

Flow-through pinout, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

PDIP (N)

20

228.702 mm² 24.33 x 9.4

SOIC (DW)

20

131.84 mm² 12.8 x 10.3

SSOP (DBQ)

20

51.9 mm² 8.65 x 6

Function and Pinout Compatible With FCT and F Logic
Reduced V_OH(Typically = 3.3 V) Versions of Equivalent FCT Functions
Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
I_off Supports Partial-Power-Down Mode Operation
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Matched Rise and Fall Times
Fully Compatible With TTL Input and Output Logic Levels
3-State Outputs
CY54FCT573T
- 32-mA Output Sink Current
- 12-mA Output Source Current
CY74FCT573T
- 64-mA Output Sink Current
- 32-mA Output Source Current

Function and Pinout Compatible With FCT and F Logic
Reduced V_OH(Typically = 3.3 V) Versions of Equivalent FCT Functions
Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
I_off Supports Partial-Power-Down Mode Operation
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Matched Rise and Fall Times
Fully Compatible With TTL Input and Output Logic Levels
3-State Outputs
CY54FCT573T
- 32-mA Output Sink Current
- 12-mA Output Source Current
CY74FCT573T
- 64-mA Output Sink Current
- 32-mA Output Source Current

The \x92FCT573T devices consist of eight latches with 3-state outputs for bus-organized applications. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches. The \x92FCT573T devices are identical to the \x92FCT373T devices, except for the flow-through pinout of the \x92FCT573T, which simplifies board design.

These devices are fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The \x92FCT573T devices consist of eight latches with 3-state outputs for bus-organized applications. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches. The \x92FCT573T devices are identical to the \x92FCT373T devices, except for the flow-through pinout of the \x92FCT573T, which simplifies board design.

These devices are fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Alle anzeigen 9

	Typ	Titel		Datum
*	Data sheet	8-Bit Latches With 3-State Outputs datasheet		01 Okt 2001
	Application note	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	15 Dez 2022
	Selection guide	Logic Guide (Rev. AB)		12 Jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		02 Dez 2015
	User guide	LOGIC Pocket Data Book (Rev. B)		16 Jan 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 Jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)		22 Jun 2004
	User guide	CYFCT Parameter Measurement Information		02 Apr 2001
	Selection guide	Advanced Bus Interface Logic Selection Guide		09 Jan 2001

Design und Entwicklung

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Evaluierungsplatine

14-24-LOGIC-EVM — Generisches Logikprodukt-Evaluierungsmodul für 14-polige bis 24-polige D-, DB-, DGV-, DW-, DYY-, NS-

Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.

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Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
PDIP (N)	20	Ultra Librarian
SOIC (DW)	20	Ultra Librarian
SSOP (DBQ)	20	Ultra Librarian

Es gelten die allgemeinen Geschäftsbedingungen von TI für Evaluierungsartikel.

CY74FCT573T

Transparente Achtfach-Latches (Typ D), mit Tri-State-Ausgängen

CY74FCT573T

Produktdetails

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