SN54AHCT74

Name: SN54AHCT74
Brand: TI
SKU: SN54AHCT74
Price: 16.835 USD

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Zweifach-Flipflops (Typ D) mit positiver Flankensteuerung, Clear und Preset

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Datenblatt

document-pdfAcrobat SNxAHCT74 Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset datasheet (Rev. R) (Englisch) PDF | HTML

SN54AHCT74

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Datenblatt

Jetzt bestellen

Produktdetails

Number of channels

2

Technology family

AHCT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

70

IOL (max) (mA)

8

IOH (max) (mA)

-8

Supply current (max) (µA)

20

Features

Balanced outputs, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-55 to 125

Rating

Military

Number of channels

2

Technology family

AHCT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

70

IOL (max) (mA)

8

IOH (max) (mA)

-8

Supply current (max) (µA)

20

Features

Balanced outputs, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-55 to 125

Rating

Military

CDIP (J)

14

130.4652 mm² 19.56 x 6.67

CFP (W)

14

58.023 mm² 9.21 x 6.3

LCCC (FK)

20

79.0321 mm² 8.89 x 8.89

Operating range of 4.5 V to 5.5 V
Low power consumption, 10-µA maximum I CC
±8-mA output drive at 5 V
Inputs are TTL-voltage compatible
Latch-up performance exceeds 250 mA per JESD 17

Operating range of 4.5 V to 5.5 V
Low power consumption, 10-µA maximum I CC
±8-mA output drive at 5 V
Inputs are TTL-voltage compatible
Latch-up performance exceeds 250 mA per JESD 17

The ’AHCT74 dual positive-edge-triggered devices are D-type flip-flops.

A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

The ’AHCT74 dual positive-edge-triggered devices are D-type flip-flops.

A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

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Technische Dokumentation

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Alle anzeigen 21

	Typ	Titel		Datum
*	Data sheet	SNxAHCT74 Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset datasheet (Rev. R)	PDF \| HTML	17 Okt 2023
*	SMD	SN54AHCT74 SMD 5962-96861		21 Jun 2016
	Application note	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	15 Dez 2022
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		26 Jul 2021
	Selection guide	Little Logic Guide 2018 (Rev. G)		06 Jul 2018
	Selection guide	Logic Guide (Rev. AB)		12 Jun 2017
	Application note	How to Select Little Logic (Rev. A)		26 Jul 2016
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		02 Dez 2015
	User guide	LOGIC Pocket Data Book (Rev. B)		16 Jan 2007
	Product overview	Design Summary for WCSP Little Logic (Rev. B)		04 Nov 2004
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 Jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)		22 Jun 2004
	Application note	Advanced High-Speed CMOS (AHC) Logic Family (Rev. C)		02 Dez 2002
	Application note	Texas Instruments Little Logic Application Report		01 Nov 2002
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		29 Aug 2002
	Design guide	AHC/AHCT Designer's Guide February 2000 (Rev. D)		24 Feb 2000
	Product overview	Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C)		01 Apr 1998
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices		01 Dez 1997
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)		01 Aug 1997
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)		01 Jun 1997
	Application note	Live Insertion		01 Okt 1996

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
CDIP (J)	14	Ultra Librarian
CFP (W)	14	Ultra Librarian
LCCC (FK)	20	Ultra Librarian

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SN54AHCT74

Zweifach-Flipflops (Typ D) mit positiver Flankensteuerung, Clear und Preset

SN54AHCT74

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