SN54ALS174

Name: SN54ALS174
Brand: TI
SKU: SN54ALS174
Price: 27.687 USD

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Hexadezimal-D-Typ-Flipflop mit Clear-Eingang

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Datenblatt

document-pdfAcrobat Hex/Quadruple D-Type Flip-Flops With Clear datasheet (Rev. E) (Englisch)

SN54ALS174

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Number of channels

6

Technology family

ALS

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

Bipolar

Output type

Push-Pull

Clock frequency (max) (MHz)

75

IOL (max) (mA)

8

IOH (max) (mA)

-0.4

Supply current (max) (µA)

19000

Features

High speed (tpd 10-50ns)

Operating temperature range (°C)

-55 to 125

Rating

Military

Number of channels

6

Technology family

ALS

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

Bipolar

Output type

Push-Pull

Clock frequency (max) (MHz)

75

IOL (max) (mA)

8

IOH (max) (mA)

-0.4

Supply current (max) (µA)

19000

Features

High speed (tpd 10-50ns)

Operating temperature range (°C)

-55 to 125

Rating

Military

CDIP (J)

16

135.3552 mm² 19.56 x 6.92

CFP (W)

16

69.319 mm² 10.3 x 6.73

LCCC (FK)

20

79.0321 mm² 8.89 x 8.89

’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs
’ALS175 and ’AS175B Contain Four Flip-Flops With Double-Rail Outputs
Buffered Clock and Direct-Clear Inputs
Applications Include:
- Buffer/Storage Registers
- Shift Registers
- Pattern Generators
Fully Buffered Outputs for Maximum Isolation From External Disturbances (’AS Only)

’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs
’ALS175 and ’AS175B Contain Four Flip-Flops With Double-Rail Outputs
Buffered Clock and Direct-Clear Inputs
Applications Include:
- Buffer/Storage Registers
- Shift Registers
- Pattern Generators
Fully Buffered Outputs for Maximum Isolation From External Disturbances (’AS Only)

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.

Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

These circuits are fully compatible for use with most TTL circuits.

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.

Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

These circuits are fully compatible for use with most TTL circuits.

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Andere D-Typ-Flipflops suchen

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Alle anzeigen 13

	Typ	Titel		Datum
*	Data sheet	Hex/Quadruple D-Type Flip-Flops With Clear datasheet (Rev. E)		23 Mai 2002
*	SMD	SN54ALS174 SMD 83019012A		21 Jun 2016
	Application note	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	15 Dez 2022
	Selection guide	Logic Guide (Rev. AB)		12 Jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		02 Dez 2015
	User guide	LOGIC Pocket Data Book (Rev. B)		16 Jan 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 Jul 2004
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		29 Aug 2002
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)		01 Aug 1997
	Application note	Designing With Logic (Rev. C)		01 Jun 1997
	Application note	Input and Output Characteristics of Digital Integrated Circuits		01 Okt 1996
	Application note	Live Insertion		01 Okt 1996
	Application note	Advanced Schottky (ALS and AS) Logic Families		01 Aug 1995

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
CDIP (J)	16	Ultra Librarian
CFP (W)	16	Ultra Librarian
LCCC (FK)	20	Ultra Librarian

Es gelten die allgemeinen Geschäftsbedingungen von TI für Evaluierungsartikel.

SN54ALS174

Hexadezimal-D-Typ-Flipflop mit Clear-Eingang

SN54ALS174

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