SN54HC373-DIE

AKTIV

Transparentes Achtfach-Latch (Typ D) mit Tri-State-Ausgängen

Produktdetails

Number of channels 8 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Operating temperature range (°C) 25 to 25 Rating Space
Number of channels 8 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Operating temperature range (°C) 25 to 25 Rating Space
DIESALE (TD) See data sheet
  • Wide Operating Voltage Range
  • High-Current 3-State True Outputs Can
    Drive Up To 15 LSTTL Loads
  • Low Power Consumption
  • Typical tpd = 13 ns
  • Low Input Current
  • Full Parallel Access for Loading

  • Wide Operating Voltage Range
  • High-Current 3-State True Outputs Can
    Drive Up To 15 LSTTL Loads
  • Low Power Consumption
  • Typical tpd = 13 ns
  • Low Input Current
  • Full Parallel Access for Loading

This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the SN54HC373-DIE are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs.

This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the SN54HC373-DIE are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels that were set up at the D inputs.

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Technische Dokumentation

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Typ Titel Datum
* Data sheet Octal Transparent D-Type Latch With 3-State Outputs, SN54HC373-DIE datasheet 10 Mai 2013
Selection guide TI Space Products (Rev. J) 12 Feb 2024
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dez 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Okt 1996
Application note Live Insertion 01 Okt 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 Mai 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design und Entwicklung

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DIESALE (TD)

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