SN54LS194A

AKTIV

Bidirektionale Universal-Schieberegister, 4 Bit

Produktdetails

Configuration Universal Bits (#) 4 Technology family LS Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 25 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Supply current (max) (µA) 63000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
Configuration Universal Bits (#) 4 Technology family LS Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 25 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Supply current (max) (µA) 63000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92 CFP (W) 16 69.319 mm² 10.3 x 6.73 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Parallel Inputs and Outputs
  • Four Operating Modes:
    • Synchronous Parallel Load
    • Right Shift
    • Left Shift
    • Do Nothing
  • Positive Edge-Triggered Clocking
  • Direct Overriding Clear

 

  • Parallel Inputs and Outputs
  • Four Operating Modes:
    • Synchronous Parallel Load
    • Right Shift
    • Left Shift
    • Do Nothing
  • Positive Edge-Triggered Clocking
  • Direct Overriding Clear

 

These bidirectional shift registers are designed to incorporate virtually all of the features a system designer may want in a shift register. The circuit contains 46 equivalent gates and features parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely:

  • Inhibit clock (do nothing)
  • Shift right (in the direction QA toward QD)
  • Shift left (in the direction QD toward QA)
  • Parallel (broadside) load

Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.

Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial input.

Clocking of the shift register is inhibited when both mode control inputs are low. The mode controls of the SN54194/SN74194 should be changed only while the clock input is high.

 

These bidirectional shift registers are designed to incorporate virtually all of the features a system designer may want in a shift register. The circuit contains 46 equivalent gates and features parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely:

  • Inhibit clock (do nothing)
  • Shift right (in the direction QA toward QD)
  • Shift left (in the direction QD toward QA)
  • Parallel (broadside) load

Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.

Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial input.

Clocking of the shift register is inhibited when both mode control inputs are low. The mode controls of the SN54194/SN74194 should be changed only while the clock input is high.

 

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Technische Dokumentation

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Alle anzeigen 11
Typ Titel Datum
* Data sheet 4-Bit Bidirectional Universal Shift Registers datasheet 01 Mär 1988
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dez 2022
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Designing with the SN54/74LS123 (Rev. A) 01 Mär 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Okt 1996
Application note Live Insertion 01 Okt 1996

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
CDIP (J) 16 Ultra Librarian
CFP (W) 16 Ultra Librarian
LCCC (FK) 20 Ultra Librarian

Bestellen & Qualität

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  • Montagestandort

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