SN54LS299

AKTIV

Universelle Schiebe-/Speicherregister, 8 Bit

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Produktdetails

Configuration Universal Bits (#) 8 Technology family LS Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 25 IOL (max) (mA) 24 IOH (max) (mA) -2.6 Supply current (max) (µA) 53000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
Configuration Universal Bits (#) 8 Technology family LS Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Bipolar Output type Push-Pull Clock frequency (MHz) 25 IOL (max) (mA) 24 IOH (max) (mA) -2.6 Supply current (max) (µA) 53000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 20 167.464 mm² 24.2 x 6.92 CFP (W) 20 90.5828 mm² 13.09 x 6.92 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Multiplexed Inputs/Outputs Provide Improved Bit Density
  • Four Modes of Operations:
    • Hold (Store)
    • Shift Left
    • Shift Right
    • Load Data
  • Operates with Outputs Enabled or at High Z
  • 3-State Outputs Drive Bus Lines Directly
  • Can Be Cascaded for N-Bit Word Lengths
  • SN54LS323 and SN74LS323 Are Similar But Have Synchronous Clear
  • Applications:
    • Stacked or Push-Down Registers Buffer Storage, and Accumulator Registers

 

  • Multiplexed Inputs/Outputs Provide Improved Bit Density
  • Four Modes of Operations:
    • Hold (Store)
    • Shift Left
    • Shift Right
    • Load Data
  • Operates with Outputs Enabled or at High Z
  • 3-State Outputs Drive Bus Lines Directly
  • Can Be Cascaded for N-Bit Word Lengths
  • SN54LS323 and SN74LS323 Are Similar But Have Synchronous Clear
  • Applications:
    • Stacked or Push-Down Registers Buffer Storage, and Accumulator Registers

 

These Schottky TTL eight-bit universal registers feature multiplexed inputs/outputs to achieve full eight-bit data handling in a single 20-pin package. Two function-select inputs and two output-control inputs can be used to choose the modes of operation listed in the function table.

Synchronous parallel loading is accomplished by taking both function-select lines, S0 and S1, high. This places the three-state outputs in a high-impedance state, which permits data that is applied on the input/output lines to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. A direct overriding input is provided to clear the register whether the outputs are enabled or off.

 

These Schottky TTL eight-bit universal registers feature multiplexed inputs/outputs to achieve full eight-bit data handling in a single 20-pin package. Two function-select inputs and two output-control inputs can be used to choose the modes of operation listed in the function table.

Synchronous parallel loading is accomplished by taking both function-select lines, S0 and S1, high. This places the three-state outputs in a high-impedance state, which permits data that is applied on the input/output lines to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. A direct overriding input is provided to clear the register whether the outputs are enabled or off.

 

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Technische Dokumentation

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Typ Titel Datum
* Data sheet 8-Bit Universal Shift/Storage Registers datasheet 01 Mär 1988
* SMD SN54LS299 SMD 78024012A 21 Jun 2016
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dez 2022
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Designing with the SN54/74LS123 (Rev. A) 01 Mär 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Okt 1996
Application note Live Insertion 01 Okt 1996

Design und Entwicklung

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Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
CDIP (J) 20 Ultra Librarian
CFP (W) 20 Ultra Librarian
LCCC (FK) 20 Ultra Librarian

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