SN54LVC14A-SP

AKTIV

Weltraumtauglicher 6-Kanal, 2-V- bis 3,6-V-Inverter mit Schmitt-Trigger-Eingängen

Produktdetails

Technology family LVC Supply voltage (min) (V) 2 Supply voltage (max) (V) 3.6 Number of channels 6 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 10 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Space Operating temperature range (°C) -55 to 125
Technology family LVC Supply voltage (min) (V) 2 Supply voltage (max) (V) 3.6 Number of channels 6 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 10 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Space Operating temperature range (°C) -55 to 125
CDIP (J) 14 130.4652 mm² 19.56 x 6.67 CFP (W) 14 58.023 mm² 9.21 x 6.3 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 2000-V human-body model (A114-A)
    • 200-V machine model (A115-A)
    • 1000-V charged-device model (C101)
  • Operate from 1.65 V to 3.6 V VCC
  • Specified from –40°C to +85°C, –40°C to 125°C, and –55°C to 125°C
  • Inputs accept voltages to 5.5 V
  • Max tpd of 6.4 ns at 3.3 V
  • Typical VOLP (output ground bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (output VOH undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 2000-V human-body model (A114-A)
    • 200-V machine model (A115-A)
    • 1000-V charged-device model (C101)
  • Operate from 1.65 V to 3.6 V VCC
  • Specified from –40°C to +85°C, –40°C to 125°C, and –55°C to 125°C
  • Inputs accept voltages to 5.5 V
  • Max tpd of 6.4 ns at 3.3 V
  • Typical VOLP (output ground bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (output VOH undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

The SN54LVC14A hex Schmitt-trigger inverter is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC14A hex Schmitt-trigger inverter is designed for 1.65-V to 3.6-V VCC operation.

The devices contain six independent inverters and perform the Boolean function Y = A.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V or 5-V system environment.

The SN54LVC14A hex Schmitt-trigger inverter is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC14A hex Schmitt-trigger inverter is designed for 1.65-V to 3.6-V VCC operation.

The devices contain six independent inverters and perform the Boolean function Y = A.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V or 5-V system environment.

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Technische Dokumentation

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Typ Titel Datum
* Data sheet SNx4LVC14A Hex Schmitt-Trigger Inverters datasheet (Rev. AC) PDF | HTML 20 Apr 2022
* SMD SN54LVC14A-SP SMD 5962-97615 08 Jul 2016
Application brief DLA Approved Optimizations for QML Products (Rev. B) PDF | HTML 23 Okt 2024
Selection guide TI Space Products (Rev. J) 12 Feb 2024
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. A) 31 Aug 2023
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Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 Nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dez 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
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Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dez 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note LVC Characterization Information 01 Dez 1996
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Design guide Low-Voltage Logic (LVC) Designer's Guide 01 Sep 1996
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Design und Entwicklung

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Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
CDIP (J) 14 Ultra Librarian
CFP (W) 14 Ultra Librarian
LCCC (FK) 20 Ultra Librarian

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