SN74ABT273

Name: SN74ABT273
Brand: TI
SKU: SN74ABT273
Price: 0.277 USD

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Flankengesteuerte Achtfach-Flipflops (Typ D) mit Clear

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Datenblatt

document-pdfAcrobat Octal Edge-Triggered D-Type Flip-Flops With Clear datasheet (Rev. B) (Englisch)

SN74ABT273

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Datenblatt

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Produktdetails

Number of channels

8

Technology family

ABT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

150

IOL (max) (mA)

64

IOH (max) (mA)

-32

Supply current (max) (µA)

30000

Features

Partial power down (Ioff), Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

8

Technology family

ABT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

150

IOL (max) (mA)

64

IOH (max) (mA)

-32

Supply current (max) (µA)

30000

Features

Partial power down (Ioff), Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

PDIP (N)

20

228.702 mm² 24.33 x 9.4

SOIC (DW)

20

131.84 mm² 12.8 x 10.3

SOP (NS)

20

98.28 mm² 12.6 x 7.8

SSOP (DB)

20

56.16 mm² 7.2 x 7.8

TSSOP (PW)

20

41.6 mm² 6.5 x 6.4

State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Plastic (N) and Ceramic (J) DIPs, and Ceramic Flat (W) Package

EPIC-IIB is a trademark of Texas Instruments Incorporated.

State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Plastic (N) and Ceramic (J) DIPs, and Ceramic Flat (W) Package

EPIC-IIB is a trademark of Texas Instruments Incorporated.

The 'ABT273 are 8-bit positive-edge-triggered D-type flip-flops with a direct clear () input. They are particularly suitable for implementing buffer and storage registers, shift registers, and pattern generators.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D input signal has no effect at the output.

The SN54ABT273 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT273 is characterized for operation from -40°C to 85°C.

The 'ABT273 are 8-bit positive-edge-triggered D-type flip-flops with a direct clear () input. They are particularly suitable for implementing buffer and storage registers, shift registers, and pattern generators.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D input signal has no effect at the output.

The SN54ABT273 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT273 is characterized for operation from -40°C to 85°C.

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Technische Dokumentation

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Alle anzeigen 20

	Typ	Titel		Datum
*	Data sheet	Octal Edge-Triggered D-Type Flip-Flops With Clear datasheet (Rev. B)		01 Jan 1997
	Application note	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	15 Dez 2022
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		26 Jul 2021
	Selection guide	Logic Guide (Rev. AB)		12 Jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		02 Dez 2015
	User guide	LOGIC Pocket Data Book (Rev. B)		16 Jan 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 Jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)		22 Jun 2004
	Application note	Quad Flatpack No-Lead Logic Packages (Rev. D)		16 Feb 2004
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		29 Aug 2002
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices		10 Mai 2002
	Selection guide	Advanced Bus Interface Logic Selection Guide		09 Jan 2001
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)		01 Aug 1997
	Application note	Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B)		01 Jun 1997
	Application note	Designing With Logic (Rev. C)		01 Jun 1997
	Application note	Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A)		01 Mär 1997
	Application note	Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A)		01 Dez 1996
	Application note	Input and Output Characteristics of Digital Integrated Circuits		01 Okt 1996
	Application note	Live Insertion		01 Okt 1996
	Application note	Understanding Advanced Bus-Interface Products Design Guide		01 Mai 1996

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Evaluierungsplatine

14-24-LOGIC-EVM — Generisches Logikprodukt-Evaluierungsmodul für 14-polige bis 24-polige D-, DB-, DGV-, DW-, DYY-, NS-

Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.

Benutzerhandbuch: PDF | HTML

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Simulationsmodell

SN74ABT273 IBIS Model (Rev. B)

SCBM081B.ZIP (16 KB) - IBIS Model

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Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
PDIP (N)	20	Ultra Librarian
SOIC (DW)	20	Ultra Librarian
SOP (NS)	20	Ultra Librarian
SSOP (DB)	20	Ultra Librarian
TSSOP (PW)	20	Ultra Librarian

Es gelten die allgemeinen Geschäftsbedingungen von TI für Evaluierungsartikel.

SN74ABT273

Flankengesteuerte Achtfach-Flipflops (Typ D) mit Clear

SN74ABT273

Produktdetails

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Design und Entwicklung

14-24-LOGIC-EVM — Generisches Logikprodukt-Evaluierungsmodul für 14-polige bis 24-polige D-, DB-, DGV-, DW-, DYY-, NS-

SN74ABT273 IBIS Model (Rev. B)

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