This 9-bit latch is designed specifically for storing the contents
of the input data bus and providing the capability of reading back
the stored data onto the input data bus. In addition, this device
provides a 3-state buffer-type output and is easily implemented in
parity applications.
The nine latches are transparent D-type latches. While the
latch-enable (LE) input is high, the Q outputs follow the data (D)
inputs. The Q outputs are in the 3-state condition when the
output-enable () input is
high.
Read back is provided through the output-enable () input. When is taken low, the data present at
the output of the data latches is allowed to pass back onto the input
data bus. When is taken high,
the output of the data latches is isolated from the D inputs. does not affect the internal
operation of the latches; however, precautions should be taken not to
create a bus conflict.
The SN74ALS992 is characterized for operation from 0°C to
70°C.
This 9-bit latch is designed specifically for storing the contents
of the input data bus and providing the capability of reading back
the stored data onto the input data bus. In addition, this device
provides a 3-state buffer-type output and is easily implemented in
parity applications.
The nine latches are transparent D-type latches. While the
latch-enable (LE) input is high, the Q outputs follow the data (D)
inputs. The Q outputs are in the 3-state condition when the
output-enable () input is
high.
Read back is provided through the output-enable () input. When is taken low, the data present at
the output of the data latches is allowed to pass back onto the input
data bus. When is taken high,
the output of the data latches is isolated from the D inputs. does not affect the internal
operation of the latches; however, precautions should be taken not to
create a bus conflict.
The SN74ALS992 is characterized for operation from 0°C to
70°C.