SN74ALVTH16374

Name: SN74ALVTH16374
Brand: TI
SKU: SN74ALVTH16374
Price: 0.679 USD

OBSOLET

Flankengesteuerte Flipflops (Typ D, 2,5/3,3 V, 16 Bit, mit Tri-State-Ausgängen

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Datenblatt

document-pdfAcrobat SN54ALVTH16374, SN74ALVTH16374 datasheet (Rev. G) (Englisch)

SN74ALVTH16374 wird nicht mehr produziert

Dieses Produkt wird nicht mehr produziert. Neue Designs sollten ein alternatives Produkt erwägen.

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Taktflankengesteuertes D-Flipflop, 16 Bit, mit Tri-State-Ausgängen Lower average drive strength (24mA)

SN74ALVCH16374

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Taktflankengesteuertes D-Flipflop, 16 Bit, mit Tri-State-Ausgängen Replacement

SN74ALVTH16374

OBSOLET

Datenblatt

Jetzt bestellen

Produktdetails

Number of channels

16

Technology family

ALVT

Supply voltage (min) (V)

2.3

Supply voltage (max) (V)

3.6

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (max) (MHz)

250

IOL (max) (mA)

64

IOH (max) (mA)

-32

Supply current (max) (µA)

5000

Features

Bus-hold, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

16

Technology family

ALVT

Supply voltage (min) (V)

2.3

Supply voltage (max) (V)

3.6

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (max) (MHz)

250

IOL (max) (mA)

64

IOH (max) (mA)

-32

Supply current (max) (µA)

5000

Features

Bus-hold, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

SSOP (DL)

48

164.358 mm² 15.88 x 10.35

TSSOP (DGG)

48

101.25 mm² 12.5 x 8.1

TVSOP (DGV)

48

62.08 mm² 9.7 x 6.4

State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus™ Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation
Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V V_CC)
Typical V_OLP (Output Ground Bounce) <0.8 V at V_CC = 3.3 V, T_A = 25°C
High Drive (-24/24 mA at 2.5-V V_CC and -32/64 mA at 3.3-V )
Power Off Disables Outputs, Permitting Live Insertion
High-Impedance State During Power Up and Power Down Prevents Driver Conflict
Uses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating
Auto3-State Eliminates Bus Current Loading When Output Exceeds V_CC + 0.5 V
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection
- Exceeds 2000 V Per MIL-STD-883, Method 3015
- Exceeds 200 V Using Machine Model
- Exceeds 1000 V Using Charged-Device Model, Robotic Method
Flow-Through Architecture Facilitates Printed Circuit Board Layout
Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package

Widebus is a trademark of Texas Instruments.

State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus™ Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation
Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V V_CC)
Typical V_OLP (Output Ground Bounce) <0.8 V at V_CC = 3.3 V, T_A = 25°C
High Drive (-24/24 mA at 2.5-V V_CC and -32/64 mA at 3.3-V )
Power Off Disables Outputs, Permitting Live Insertion
High-Impedance State During Power Up and Power Down Prevents Driver Conflict
Uses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating
Auto3-State Eliminates Bus Current Loading When Output Exceeds V_CC + 0.5 V
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection
- Exceeds 2000 V Per MIL-STD-883, Method 3015
- Exceeds 200 V Using Machine Model
- Exceeds 1000 V Using Charged-Device Model, Robotic Method
Flow-Through Architecture Facilitates Printed Circuit Board Layout
Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package

Widebus is a trademark of Texas Instruments.

The 'ALVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-V or 3.3-V V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When V_CC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ALVTH16374 is characterized for operation over the full military temperature range of -55°C to 125°C.

The SN74ALVTH16374 is characterized for operation from -40°C to 85°C.