SN74ALVTH16821

Name: SN74ALVTH16821
Brand: TI
SKU: SN74ALVTH16821
Price: 2.039 USD

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Flipflops mit Bus-Schnittstelle, 2,5/3,3 V, 20 Bit, mit Tri-State-Ausgängen

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Datenblatt

document-pdfAcrobat 2.5-V/3.3-V 20-Bit Bus-Interface Flip-Flops With 3-State Outputs datasheet (Rev. E) (Englisch)

SN74ALVTH16821 wird nicht mehr produziert

Dieses Produkt wird nicht mehr produziert. Neue Designs sollten ein alternatives Produkt erwägen.

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Selbe Funktionalität wie der verglichene Baustein bei gleicher Anschlussbelegung

SN74ALVCH16821

AKTIV

Bus-Schnittstellen-Flipflop, 3,3 V, 20 Bit, mit Tri-State-Ausgängen Replacement

SN74ALVTH16821

OBSOLET

Datenblatt

Jetzt bestellen

Produktdetails

Number of channels

20

Technology family

ALVT

Supply voltage (min) (V)

2.3

Supply voltage (max) (V)

3.6

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (max) (MHz)

150

IOL (max) (mA)

64

IOH (max) (mA)

-32

Supply current (max) (µA)

5000

Features

Bus-hold, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

20

Technology family

ALVT

Supply voltage (min) (V)

2.3

Supply voltage (max) (V)

3.6

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (max) (MHz)

150

IOL (max) (mA)

64

IOH (max) (mA)

-32

Supply current (max) (µA)

5000

Features

Bus-hold, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

SSOP (DL)

56

190.647 mm² 18.42 x 10.35

TSSOP (DGG)

56

113.4 mm² 14 x 8.1

TVSOP (DGV)

56

72.32 mm² 11.3 x 6.4

State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus^TM Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation
Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V V_CC)
Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
High-Drive (-24/24 mA at 2.5-V and
-32/64 mA at 3.3-V V_CC)
Power Off Disables Outputs, Permitting Live Insertion
High-Impedance State During Power Up and Power Down Prevents Driver Conflict
Uses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating
Auto3-State Eliminates Bus Current Loading When Output Exceeds V_CC + 0.5 V
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model; and Exceeds 1000 V Using Charged-Device Model, Robotic Method
Flow-Through Architecture Facilitates Printed Circuit Board Layout
Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package
Widebus is a trademark of Texas Instruments Incorporated.

State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus^TM Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation
Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V V_CC)
Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
High-Drive (-24/24 mA at 2.5-V and
-32/64 mA at 3.3-V V_CC)
Power Off Disables Outputs, Permitting Live Insertion
High-Impedance State During Power Up and Power Down Prevents Driver Conflict
Uses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating
Auto3-State Eliminates Bus Current Loading When Output Exceeds V_CC + 0.5 V
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model; and Exceeds 1000 V Using Charged-Device Model, Robotic Method
Flow-Through Architecture Facilitates Printed Circuit Board Layout
Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package
Widebus is a trademark of Texas Instruments Incorporated.

The 'ALVTH16821 devices are 20-bit bus-interface flip-flops with 3-state outputs designed for 2.5-V or 3.3-V V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The devices can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20-bit flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the D inputs.

A buffered output-enable (OE\) input can be used to place the ten outputs in either a normal logic state (high or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

When V_CC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN54ALVTH16821 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16821 is characterized for operation from -40°C to 85°C.

The 'ALVTH16821 devices are 20-bit bus-interface flip-flops with 3-state outputs designed for 2.5-V or 3.3-V V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

The devices can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20-bit flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK), the flip-flops store the logic levels set up at the D inputs.

A buffered output-enable (OE\) input can be used to place the ten outputs in either a normal logic state (high or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

When V_CC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN54ALVTH16821 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16821 is characterized for operation from -40°C to 85°C.

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	Typ	Titel		Datum
*	Data sheet	2.5-V/3.3-V 20-Bit Bus-Interface Flip-Flops With 3-State Outputs datasheet (Rev. E)		08 Jan 1999

SN74ALVTH16821

Flipflops mit Bus-Schnittstelle, 2,5/3,3 V, 20 Bit, mit Tri-State-Ausgängen

Selbe Funktionalität wie der verglichene Baustein bei gleicher Anschlussbelegung

SN74ALVTH16821

Produktdetails

Technische Dokumentation

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