SN74AUP2G80

Name: SN74AUP2G80
Brand: TI
SKU: SN74AUP2G80
Price: 0.105 USD

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Energieeffizientes Zweifachflipflop (Typ D) mit positiver Flankensteuerung

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Datenblatt

document-pdfAcrobat SN74AUP2G80 Low-Power Dual Positive-Edge-Triggered D-Type Flip-Flop datasheet (Rev. A) (Englisch)

SN74AUP2G80

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Datenblatt

Jetzt bestellen

Produktdetails

Number of channels

2

Technology family

AUP

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

3.6

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

260

IOL (max) (mA)

4

IOH (max) (mA)

-4

Supply current (max) (µA)

0.9

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

2

Technology family

AUP

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

3.6

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

260

IOL (max) (mA)

4

IOH (max) (mA)

-4

Supply current (max) (µA)

0.9

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

UQFN (RSE)

8

2.25 mm² 1.5 x 1.5

VSSOP (DCU)

8

6.2 mm² 2 x 3.1

X2SON (DQE)

8

1.4 mm² 1.4 x 1

Available in the Texas Instruments NanoStar™ Package
Low Static-Power Consumption
(I_CC = 0.9 µA Maximum)
Low Dynamic-Power Consumption
(C_pd = 4.3 pF Typ at 3.3 V)
Low Input Capacitance (C_i = 1.5 pF Typical)
Low Noise – Overshoot and Undershoot
<10% of V_CC
I_off Supports Partial-Power-Down Mode Operation
Wide Operating V_CC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
t_pd = 4.4 ns Maximum at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
  (A114-B, Class II)
- 1000-V Charged-Device Model (C101)

Available in the Texas Instruments NanoStar™ Package
Low Static-Power Consumption
(I_CC = 0.9 µA Maximum)
Low Dynamic-Power Consumption
(C_pd = 4.3 pF Typ at 3.3 V)
Low Input Capacitance (C_i = 1.5 pF Typical)
Low Noise – Overshoot and Undershoot
<10% of V_CC
I_off Supports Partial-Power-Down Mode Operation
Wide Operating V_CC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
t_pd = 4.4 ns Maximum at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
  (A114-B, Class II)
- 1000-V Charged-Device Model (C101)

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire V_CC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire V_CC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Alle anzeigen 7

	Typ	Titel		Datum
*	Data sheet	SN74AUP2G80 Low-Power Dual Positive-Edge-Triggered D-Type Flip-Flop datasheet (Rev. A)		31 Mär 2010
	Application note	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	15 Dez 2022
	Application brief	Understanding Schmitt Triggers (Rev. A)	PDF \| HTML	22 Mai 2019
	Selection guide	Little Logic Guide 2018 (Rev. G)		06 Jul 2018
	Selection guide	Logic Guide (Rev. AB)		12 Jun 2017
	Application note	How to Select Little Logic (Rev. A)		26 Jul 2016
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 Jul 2004

Design und Entwicklung

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Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
UQFN (RSE)	8	Ultra Librarian
VSSOP (DCU)	8	Ultra Librarian
X2SON (DQE)	8	Ultra Librarian

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SN74AUP2G80

Energieeffizientes Zweifachflipflop (Typ D) mit positiver Flankensteuerung

SN74AUP2G80

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