SN74AVC16373

Name: SN74AVC16373
Brand: TI
SKU: SN74AVC16373
Price: 1.957 USD

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Transparentes D-Latch, 16 Bit, mit Tri-State-Ausgängen

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Datenblatt

document-pdfAcrobat 16-Bit Transparent D-Type Latch With 3-State Outputs datasheet (Rev. H) (Englisch)

Fehlerverzeichnis

document-pdfAcrobat
Datasheet Errata for SN74AVC16373 Device Type (Englisch)

SN74AVC16373

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Datenblatt

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Produktdetails

Number of channels

16

Technology family

AVC

Supply voltage (min) (V)

1.4

Supply voltage (max) (V)

3.6

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

200

IOL (max) (mA)

12

IOH (max) (mA)

-12

Supply current (max) (µA)

40

Features

Balanced outputs, Flow-through pinout, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

16

Technology family

AVC

Supply voltage (min) (V)

1.4

Supply voltage (max) (V)

3.6

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

200

IOL (max) (mA)

12

IOH (max) (mA)

-12

Supply current (max) (µA)

40

Features

Balanced outputs, Flow-through pinout, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

TSSOP (DGG)

48

101.25 mm² 12.5 x 8.1

TVSOP (DGV)

48

62.08 mm² 9.7 x 6.4

Member of the Texas Instruments Widebus™ Family
EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
DOC™ (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
Dynamic Drive Capability Is Equivalent to Standard Outputs With I_OH and I_OL of ±24 mA at 2.5-V V_CC
Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
I_off Supports Partial-Power-Down Mode Operation
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
Package Options Include Plastic Thin Shrink Small-Outline (DGG) and Thin Very Small-Outline (DGV) Packages

2Widebus, EPIC, DOC are trademarks of Texas Instruments.

Member of the Texas Instruments Widebus™ Family
EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
DOC™ (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
Dynamic Drive Capability Is Equivalent to Standard Outputs With I_OH and I_OL of ±24 mA at 2.5-V V_CC
Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
I_off Supports Partial-Power-Down Mode Operation
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
Package Options Include Plastic Thin Shrink Small-Outline (DGG) and Thin Very Small-Outline (DGV) Packages

2Widebus, EPIC, DOC are trademarks of Texas Instruments.

A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical V_OL vs I_OL and V_OH vs I_OH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry Technology and Applications, literature number SCEA009.

This 16-bit transparent D-type latch is operational at 1.2-V to 3.6-V V_CC, but is designed specifically for 1.65-V to 3.6-V V_CC operation.

The SN74AVC16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74AVC16373 is characterized for operation from –40°C to 85°C.

A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical V_OL vs I_OL and V_OH vs I_OH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry Technology and Applications, literature number SCEA009.

This 16-bit transparent D-type latch is operational at 1.2-V to 3.6-V V_CC, but is designed specifically for 1.65-V to 3.6-V V_CC operation.

The SN74AVC16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74AVC16373 is characterized for operation from –40°C to 85°C.

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	Typ	Titel		Datum
*	Data sheet	16-Bit Transparent D-Type Latch With 3-State Outputs datasheet (Rev. H)		12 Sep 2008
*	Errata	Datasheet Errata for SN74AVC16373 Device Type		06 Nov 2008
	Application note	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	15 Dez 2022
	Selection guide	Logic Guide (Rev. AB)		12 Jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		02 Dez 2015
	Application note	Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B)		30 Apr 2015
	User guide	LOGIC Pocket Data Book (Rev. B)		16 Jan 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 Jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)		22 Jun 2004
	More literature	LCD Module Interface Application Clip		09 Mai 2003
	User guide	AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C)		20 Aug 2002
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards		13 Jun 2002
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)		22 Mai 2002
	Application note	Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B)		07 Jul 1999
	Application note	AVC Logic Family Technology and Applications (Rev. A)		26 Aug 1998

Design und Entwicklung

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SN74AVC16373 IBIS Model

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Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
TSSOP (DGG)	48	Ultra Librarian
TVSOP (DGV)	48	Ultra Librarian

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SN74AVC16373

Transparentes D-Latch, 16 Bit, mit Tri-State-Ausgängen

SN74AVC16373

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