Produktdetails

Function Counter Bits (#) 4 Technology family LS Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Bipolar Output type Push-Pull Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
Function Counter Bits (#) 4 Technology family LS Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Bipolar Output type Push-Pull Features High speed (tpd 10-50ns) Operating temperature range (°C) 0 to 70 Rating Catalog
PDIP (N) 14 181.42 mm² 19.3 x 9.4 SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8
  • Dual Versions of the Popular '90A, 'LS90 and '93A, 'LS93
  • '390, 'LS390 … Individual Clocks for A and B Flip-Flops Provide Dual ÷ 2 and ÷ 5 Counters
  • '393, 'LS393 … Dual 4-Bit Binary Counter with Individual Clocks
  • All Have Direct Clear for Each 4-Bit Counter
  • Dual 4-Bit Versions Can Significantly Improve System Densities by Reducing Counter Package Count by 50%
  • Typical Maximum Count Frequency … 35 MHz
  • Buffered Outputs Reduce Possibility of Collector Commutation

 

  • Dual Versions of the Popular '90A, 'LS90 and '93A, 'LS93
  • '390, 'LS390 … Individual Clocks for A and B Flip-Flops Provide Dual ÷ 2 and ÷ 5 Counters
  • '393, 'LS393 … Dual 4-Bit Binary Counter with Individual Clocks
  • All Have Direct Clear for Each 4-Bit Counter
  • Dual 4-Bit Versions Can Significantly Improve System Densities by Reducing Counter Package Count by 50%
  • Typical Maximum Count Frequency … 35 MHz
  • Buffered Outputs Reduce Possibility of Collector Commutation

 

Each of these monolithic circuits contains eight master-slave flip-flops and additional gating to implement two individual four-bit counters in a single package. The '390 and 'LS390 incorporate dual divide-by-two and divide-by-five counters, which can be used to implement cycle lengths equal to any whole and/or cumulative multiples of 2 and/or 5 up to divide-by-100. When connected as a bi-quinary counter, the separate divide-by-two circuit can be used to provide symmetry (a square wave) at the final output stage. The '393 and 'LS393 each comprise two independent four-bit binary counters each having a clear and a clock input. N-bit binary counters can be implemented with each package providing the capability of divide-by-256. The '390, 'LS390, '393, and 'LS393 have parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system-timing signals. Series 54 and Series 54LS circuits are characterized for operation over the full military temperature range of -55°C to 125°C; Series 74 and Series 74LS circuits are characterized for operation from 0°C to 70°C.

 

Each of these monolithic circuits contains eight master-slave flip-flops and additional gating to implement two individual four-bit counters in a single package. The '390 and 'LS390 incorporate dual divide-by-two and divide-by-five counters, which can be used to implement cycle lengths equal to any whole and/or cumulative multiples of 2 and/or 5 up to divide-by-100. When connected as a bi-quinary counter, the separate divide-by-two circuit can be used to provide symmetry (a square wave) at the final output stage. The '393 and 'LS393 each comprise two independent four-bit binary counters each having a clear and a clock input. N-bit binary counters can be implemented with each package providing the capability of divide-by-256. The '390, 'LS390, '393, and 'LS393 have parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system-timing signals. Series 54 and Series 54LS circuits are characterized for operation over the full military temperature range of -55°C to 125°C; Series 74 and Series 74LS circuits are characterized for operation from 0°C to 70°C.

 

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Typ Titel Datum
* Data sheet Dual 4-Bit Decade And Binary Counters datasheet 01 Mär 1988
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Designing with the SN54/74LS123 (Rev. A) 01 Mär 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Okt 1996
Application note Live Insertion 01 Okt 1996

Design und Entwicklung

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Evaluierungsplatine

14-24-LOGIC-EVM — Generisches Logikprodukt-Evaluierungsmodul für 14-polige bis 24-polige D-, DB-, DGV-, DW-, DYY-, NS-

Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.

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Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
PDIP (N) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian

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