DS90LV804

ACTIVE

4-channel 800-Mbps LVDS buffer/repeater

Product details

Function Buffer Protocols LVDS Number of transmitters 4 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 800 Input signal CML, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Buffer Protocols LVDS Number of transmitters 4 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 800 Input signal CML, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
WQFN (RTV) 32 25 mm² 5 x 5
  • 800 Mbps Data Rate per Channel
  • Low Output Skew and Jitter
  • LVDS/CML/LVPECL Compatible Input, LVDS Output
  • On-Chip 100Ω Input and Output Termination
  • 12 kV ESD Protection on LVDS Outputs
  • Single 3.3V Supply
  • Very Low Power Consumption
  • Industrial -40 to +85°C Temperature Range
  • Small WQFN Package Footprint

All trademarks are the property of their respective owners.

  • 800 Mbps Data Rate per Channel
  • Low Output Skew and Jitter
  • LVDS/CML/LVPECL Compatible Input, LVDS Output
  • On-Chip 100Ω Input and Output Termination
  • 12 kV ESD Protection on LVDS Outputs
  • Single 3.3V Supply
  • Very Low Power Consumption
  • Industrial -40 to +85°C Temperature Range
  • Small WQFN Package Footprint

All trademarks are the property of their respective owners.

The DS90LV804 is a four channel 800 Mbps LVDS buffer/repeater. In many large systems, signals are distributed across cables and signal integrity is highly dependent on the data rate, cable type, length, and the termination scheme.

In order to maximize signal integrity, the DS90LV804 features both an internal input and output (source) termination to eliminate these extra components from the board, and to also place the terminations as close as possible to receiver inputs and driver output. This is especially significant when driving longer cables.

The DS90LV804, available in the WQFN (Leadless Leadframe Package) package, minimizes the footprint, and improves system performance.

An output enable pin is provided, which allows the user to place the LVDS outputs and internal biasing generators in a TRI-STATE, low power mode.

The differential inputs interface to LVDS, and Bus LVDS signals such as those on TI's 10-, 16-, and 18- bit Bus LVDS SerDes, as well as CML and LVPECL. The differential inputs are internally terminated with a 100Ω resistor to improve performance and minimize board space. This function is especially useful for boosting signals over lossy cables or point-to-point backplane configurations.

The DS90LV804 is a four channel 800 Mbps LVDS buffer/repeater. In many large systems, signals are distributed across cables and signal integrity is highly dependent on the data rate, cable type, length, and the termination scheme.

In order to maximize signal integrity, the DS90LV804 features both an internal input and output (source) termination to eliminate these extra components from the board, and to also place the terminations as close as possible to receiver inputs and driver output. This is especially significant when driving longer cables.

The DS90LV804, available in the WQFN (Leadless Leadframe Package) package, minimizes the footprint, and improves system performance.

An output enable pin is provided, which allows the user to place the LVDS outputs and internal biasing generators in a TRI-STATE, low power mode.

The differential inputs interface to LVDS, and Bus LVDS signals such as those on TI's 10-, 16-, and 18- bit Bus LVDS SerDes, as well as CML and LVPECL. The differential inputs are internally terminated with a 100Ω resistor to improve performance and minimize board space. This function is especially useful for boosting signals over lossy cables or point-to-point backplane configurations.

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Technical documentation

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Type Title Date
* Data sheet DS90LV804 4-Channel 800 Mbps LVDS Buffer/Repeater datasheet (Rev. L) 16 May 2013
Application note Signaling Rate vs. Distance for Differential Buffers 26 Jan 2010
White paper Making the Most of Your LVDS - 5 Tips for Buffering Signal Integrity Headaches 01 Aug 2001
Application note An Overview of LVDS Technology 05 Oct 1998

Design & development

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Simulation model

DS90LV804 IBIS Model

SNLM025.ZIP (11 KB) - IBIS Model
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