ADC12QS065

ACTIVO

Convertidor analógico a digital (ADC) de cuatro canales, 12 bits y 65 MSPS

Detalles del producto

Sample rate (max) (Msps) 65 Resolution (bps) 12 Number of input channels 4 Interface type Serial LVDS Analog input BW (MHz) 300 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 828 Architecture Pipeline SNR (dB) 69.3 ENOB (bit) 11.2 SFDR (dB) 83.3 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 65 Resolution (bps) 12 Number of input channels 4 Interface type Serial LVDS Analog input BW (MHz) 300 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 828 Architecture Pipeline SNR (dB) 69.3 ENOB (bit) 11.2 SFDR (dB) 83.3 Operating temperature range (°C) -40 to 85 Input buffer No
WQFN (NKA) 60 81 mm² 9 x 9
  • Single +3.3V Supply Operation
  • Internal Sample-and-Hold and Internal Reference
  • Low Power Consumption
  • Power Down Mode
  • Clock and Data Frame Timing
  • 780 Mbps Serial LVDS Data Rate (at 65 MHz Clock)
  • LVDS Serial Output Rated for 100 Ohm Load

Key Specifications

  • Resolution: 12 Bits
  • DNL: ±0.3 LSB (Typ)
  • SNR (fIN = 5 MHz): 69 dB (Typ)
  • SFDR (fIN = 5 MHz): 83 dB (Typ)
  • ENOB (at Nyquist): 11 Bits (Typ)
  • Power Consumption
    • Operating, 65 MSPS, per ADC: 200 mW (Typ)
    • Power Down Mode: < 3 mW (Typ)

All trademarks are the property of their respective owners.

  • Single +3.3V Supply Operation
  • Internal Sample-and-Hold and Internal Reference
  • Low Power Consumption
  • Power Down Mode
  • Clock and Data Frame Timing
  • 780 Mbps Serial LVDS Data Rate (at 65 MHz Clock)
  • LVDS Serial Output Rated for 100 Ohm Load

Key Specifications

  • Resolution: 12 Bits
  • DNL: ±0.3 LSB (Typ)
  • SNR (fIN = 5 MHz): 69 dB (Typ)
  • SFDR (fIN = 5 MHz): 83 dB (Typ)
  • ENOB (at Nyquist): 11 Bits (Typ)
  • Power Consumption
    • Operating, 65 MSPS, per ADC: 200 mW (Typ)
    • Power Down Mode: < 3 mW (Typ)

All trademarks are the property of their respective owners.

The ADC12QS065 is a low power, high performance CMOS 4-channel analog-to-digital converter with LVDS serialized outputs. The ADC12QS065 digitizes signals to 12 bits resolution at sampling rates up to 65 MSPS while consuming a typical 200 mW/ADC from a single 3.3V supply. Sampled data is transformed into high speed serial LVDS output data streams. Clock and frame LVDS pairs aid in data capture. The ADC12QS065’s six differential pairs transmit data over backplanes or cable and also make PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost.

No missing codes performance is ensured over the full operating temperature range. The pipeline ADC architecture achieves 11 Effective Bits over the entire Nyquist band at 65 MSPS.

When not converting, power consumption can be reduced by pulling the PD (Power Down) pin high, placing the converter into a low power state where it typically consumes less than 3 mW total, and from which recovery is less than 5 ms. The ADC12QS065's speed, resolution and single supply operation makes it well suited for a variety of applications in ultrasound, imaging, video and communications. Operating over the industrial (-40°C to +85°C) temperature range, the ADC12QS065 is available in a 60-pin WQFN package with exposed pad (9x9x0.8mm, 0.5mm pin pitch).

The ADC12QS065 is a low power, high performance CMOS 4-channel analog-to-digital converter with LVDS serialized outputs. The ADC12QS065 digitizes signals to 12 bits resolution at sampling rates up to 65 MSPS while consuming a typical 200 mW/ADC from a single 3.3V supply. Sampled data is transformed into high speed serial LVDS output data streams. Clock and frame LVDS pairs aid in data capture. The ADC12QS065’s six differential pairs transmit data over backplanes or cable and also make PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost.

No missing codes performance is ensured over the full operating temperature range. The pipeline ADC architecture achieves 11 Effective Bits over the entire Nyquist band at 65 MSPS.

When not converting, power consumption can be reduced by pulling the PD (Power Down) pin high, placing the converter into a low power state where it typically consumes less than 3 mW total, and from which recovery is less than 5 ms. The ADC12QS065's speed, resolution and single supply operation makes it well suited for a variety of applications in ultrasound, imaging, video and communications. Operating over the industrial (-40°C to +85°C) temperature range, the ADC12QS065 is available in a 60-pin WQFN package with exposed pad (9x9x0.8mm, 0.5mm pin pitch).

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Documentación técnica

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Tipo Título Fecha
* Data sheet ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs datasheet (Rev. I) 12 abr 2013
Application note Understanding High-Speed Signals, Clocks, and Data Capture 18 oct 2005
White paper Data Converter Serial LVDS Interface Improves Board Routing 01 ago 2005

Diseño y desarrollo

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Modelo de simulación

ADC12QS065 IBIS Model

SNOM006.ZIP (5 KB) - IBIS Model
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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WQFN (NKA) 60 Ultra Librarian

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