CD74HCT7046A

Name: CD74HCT7046A
Brand: TI
SKU: CD74HCT7046A
Price: 1.34 USD

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Bucle de bloqueo de fase CMOS Logic de alta velocidad con VCO y detector de bloqueo

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document-pdfAcrobat CD74HC7046A, CD74HCT7046A datasheet (Rev. C) (Inglés)

CD74HCT7046A

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Detalles del producto

Technology family

HCT

Bits (#)

1

Rating

Catalog

Operating temperature range (°C)

-55 to 125

Technology family

HCT

Bits (#)

1

Rating

Catalog

Operating temperature range (°C)

-55 to 125

PDIP (N)

16

181.42 mm² 19.3 x 9.4

SOIC (D)

16

59.4 mm² 9.9 x 6

Center Frequency of 18MHz (Typ) at V_CC = 5V, Minimum Center Frequency of 12MHz at V_CC = 4.5V
Choice of Two Phase Comparators
- Exclusive-OR
- Edge-Triggered JK Flip-Flop
Excellent VCO Frequency Linearity
VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption
Minimal Frequency Drift
Zero Voltage Offset Due to Op-Amp Buffer
Operating Power-Supply Voltage Range
- VCO Section...3V to 6V
- Digital Section...2V to 6V
Fanout (Over Temperature Range)
- Standard Outputs...10 LSTTL Loads
- Bus Driver Outputs...15 LSTTL Loads
Wide Operating Temperature Range... –55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
Applications
- FM Modulation and Demodulation
- Frequency Synthesis and Multiplication
- Frequency Discrimination
- Tone Decoding
- Data Synchronization and Conditioning
- Voltage-to-Frequency Conversion
- Motor-Speed Control
- Related Literature
  - AN8823, CMOS Phase-Locked-Loop Application Using the CD74HC/HCT7046A and CD74HC/HCT7046A

Center Frequency of 18MHz (Typ) at V_CC = 5V, Minimum Center Frequency of 12MHz at V_CC = 4.5V
Choice of Two Phase Comparators
- Exclusive-OR
- Edge-Triggered JK Flip-Flop
Excellent VCO Frequency Linearity
VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption
Minimal Frequency Drift
Zero Voltage Offset Due to Op-Amp Buffer
Operating Power-Supply Voltage Range
- VCO Section...3V to 6V
- Digital Section...2V to 6V
Fanout (Over Temperature Range)
- Standard Outputs...10 LSTTL Loads
- Bus Driver Outputs...15 LSTTL Loads
Wide Operating Temperature Range... –55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
Applications
- FM Modulation and Demodulation
- Frequency Synthesis and Multiplication
- Frequency Discrimination
- Tone Decoding
- Data Synchronization and Conditioning
- Voltage-to-Frequency Conversion
- Motor-Speed Control
- Related Literature
  - AN8823, CMOS Phase-Locked-Loop Application Using the CD74HC/HCT7046A and CD74HC/HCT7046A

The CD74HC7046A and CD74HCT7046A high-speed silicon-gate CMOS devices, specified in compliance with JEDEC Standard No. 7A, are phase-locked-loop (PLL) circuits that contain a linear voltage-controlled oscillator (VCO), two-phase comparators (PC1, PC2), and a lock detector. A signal input and a comparator input are common to each comparator. The lock detector gives a HIGH level at pin 1 (LD) when the PLL is locked. The lock detector capacitor must be connected between pin 15 (C_LD) and pin 8 (Gnd). For a frequency range of 100kHz to 10MHz, the lock detector capacitor should be 1000pF to 10pF, respectively.

The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 7046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.

The CD74HC7046A and CD74HCT7046A high-speed silicon-gate CMOS devices, specified in compliance with JEDEC Standard No. 7A, are phase-locked-loop (PLL) circuits that contain a linear voltage-controlled oscillator (VCO), two-phase comparators (PC1, PC2), and a lock detector. A signal input and a comparator input are common to each comparator. The lock detector gives a HIGH level at pin 1 (LD) when the PLL is locked. The lock detector capacitor must be connected between pin 15 (C_LD) and pin 8 (Gnd). For a frequency range of 100kHz to 10MHz, the lock detector capacitor should be 1000pF to 10pF, respectively.

The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 7046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.

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Documentación técnica

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	Tipo	Título	Fecha
*	Data sheet	CD74HC7046A, CD74HCT7046A datasheet (Rev. C)	16 oct 2003
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	26 jul 2021
	Selection guide	Logic Guide (Rev. AB)	12 jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 dic 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 ene 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 jul 2004
	User guide	Signal Switch Data Book (Rev. A)	14 nov 2003
	Application note	CMOS Phase-Locked-Loop Applications (Rev. B)	19 sep 2002
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 ago 2002
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	01 jun 1997
	Application note	Designing With Logic (Rev. C)	01 jun 1997
	Application note	SN54/74HCT CMOS Logic Family Applications and Restrictions	01 may 1996
	Application note	Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc	01 abr 1996

Diseño y desarrollo

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Encapsulado	Pines	Símbolos CAD, huellas y modelos 3D
PDIP (N)	16	Ultra Librarian
SOIC (D)	16	Ultra Librarian

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CD74HCT7046A

Bucle de bloqueo de fase CMOS Logic de alta velocidad con VCO y detector de bloqueo

CD74HCT7046A

Detalles del producto

Documentación técnica

Diseño y desarrollo

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

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