CDC3S04

Name: CDC3S04
Brand: TI
SKU: CDC3S04
Price: 1.346 USD

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Búfer de reloj de onda senoidal cuádruple con LDO

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Hoja de datos

document-pdfAcrobat CDC3S04 Quad Sine-Wave Clock Buffer with LDO. datasheet (Rev. C) (Inglés)

CDC3S04

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Detalles del producto

Function

Single-ended

Additive RMS jitter (typ) (fs)

300

Output frequency (max) (MHz)

52

Number of outputs

4

Output supply voltage (V)

1.8

Core supply voltage (V)

1.8

Output skew (ps)

50

Features

SINE wave

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

SINE

Input type

SINE

Function

Single-ended

Additive RMS jitter (typ) (fs)

300

Output frequency (max) (MHz)

52

Number of outputs

4

Output supply voltage (V)

1.8

Core supply voltage (V)

1.8

Output skew (ps)

50

Features

SINE wave

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

SINE

Input type

SINE

DSBGA (YFF)

20

3.96 mm² 1.8 x 2.2

1:4 Low-Jitter Clock Buffer
Single-Ended Sine-Wave Clock Input and Outputs
Ultralow Phase Noise and Standby Current
Individual Clock Request Inputs for Each Output
On-Chip Low-Dropout Output (LDO) for Low-Noise TCXO Supply
Serial I²C Interface (Compatible With High-Speed Mode,
3.4 Mbit/s)
1.8-V Device Power Supply
Wide Temperature Range, –40°C to 85°C
ESD Protection: 2 KV HBM, 750 V CDM, and 100 V MM
Small 20-Pin Chip-Scale Package: 0.4-mm Pitch WCSP (1.6 mm × 2 mm)

1:4 Low-Jitter Clock Buffer
Single-Ended Sine-Wave Clock Input and Outputs
Ultralow Phase Noise and Standby Current
Individual Clock Request Inputs for Each Output
On-Chip Low-Dropout Output (LDO) for Low-Noise TCXO Supply
Serial I²C Interface (Compatible With High-Speed Mode,
3.4 Mbit/s)
1.8-V Device Power Supply
Wide Temperature Range, –40°C to 85°C
ESD Protection: 2 KV HBM, 750 V CDM, and 100 V MM
Small 20-Pin Chip-Scale Package: 0.4-mm Pitch WCSP (1.6 mm × 2 mm)

The CDC3S04 is a four-channel low-power low-jitter sine-wave clock buffer. It can be used to buffer a single master clock to multiple peripherals. The four sine-wave outputs (CLK1–CLK4) are designed for minimal channel-to-channel skew and ultralow additive output jitter.

Each output has its own clock request inputs which enables the dedicated clock output. These clock requests are active-high (can also be changed to be active-low via I²C), and an output signal is generated that can be sent back to the master clock to request the clock (MCLK_REQ). MCKL_REQ is an open-source output and supports the wired-OR function (default mode). It needs an external pulldown resistor. MCKL_REQ can be changed to wired-AND or push-pull functionality via I²C.

The CDC3S04 also provides an I²C interface (Hs-mode) that can be used to enable or disable the outputs, select the polarity of the REQ inputs, and allow control of internal decoding.

The CDC3S04 features an on-chip high-performance LDO that accepts voltages from 2.3 V to 5.5 V and outputs a 1.8-V supply. This 1.8-V supply can be used to power an external 1.8-V TCXO. It can be enabled or disabled for power saving at the TCXO.

A low signal at the RESET input switches the outputs CLK1 and CLK4 into the default state. In this configuration, CLK1 and CLK4 are ON (see ); the remaining device function is not affected. Also, the RESET input provides a glitch filter which rejects spikes of typical 300 ns on the RESET line to preserve false reset. A complete device reset to the default condition can be initiated by a power-up cycle of V_{DD_DIG}.

The CDC3S04 operates from two 1.8-V supplies. There is a core supply (VDD_DIG/GND_DIG) for the core logic and a low-noise analog supply (VDD_ANA/GND_ANA) for the sine-wave outputs. The CDC3S04 is designed for sequence-less power up. Both supply voltages may be applied in any order.

The CDC3S04 is offered in a 0.4-mm pitch WCSP package (1.6 mm × 2 mm) and is optimized for low standby current (0.5 µA). It is characterized for operation from –40°C to 85°C.

The CDC3S04 is a four-channel low-power low-jitter sine-wave clock buffer. It can be used to buffer a single master clock to multiple peripherals. The four sine-wave outputs (CLK1–CLK4) are designed for minimal channel-to-channel skew and ultralow additive output jitter.

Each output has its own clock request inputs which enables the dedicated clock output. These clock requests are active-high (can also be changed to be active-low via I²C), and an output signal is generated that can be sent back to the master clock to request the clock (MCLK_REQ). MCKL_REQ is an open-source output and supports the wired-OR function (default mode). It needs an external pulldown resistor. MCKL_REQ can be changed to wired-AND or push-pull functionality via I²C.

The CDC3S04 also provides an I²C interface (Hs-mode) that can be used to enable or disable the outputs, select the polarity of the REQ inputs, and allow control of internal decoding.

The CDC3S04 features an on-chip high-performance LDO that accepts voltages from 2.3 V to 5.5 V and outputs a 1.8-V supply. This 1.8-V supply can be used to power an external 1.8-V TCXO. It can be enabled or disabled for power saving at the TCXO.

A low signal at the RESET input switches the outputs CLK1 and CLK4 into the default state. In this configuration, CLK1 and CLK4 are ON (see ); the remaining device function is not affected. Also, the RESET input provides a glitch filter which rejects spikes of typical 300 ns on the RESET line to preserve false reset. A complete device reset to the default condition can be initiated by a power-up cycle of V_{DD_DIG}.

The CDC3S04 operates from two 1.8-V supplies. There is a core supply (VDD_DIG/GND_DIG) for the core logic and a low-noise analog supply (VDD_ANA/GND_ANA) for the sine-wave outputs. The CDC3S04 is designed for sequence-less power up. Both supply voltages may be applied in any order.

The CDC3S04 is offered in a 0.4-mm pitch WCSP package (1.6 mm × 2 mm) and is optimized for low standby current (0.5 µA). It is characterized for operation from –40°C to 85°C.

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Documentación técnica

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	Tipo	Título	Fecha
*	Data sheet	CDC3S04 Quad Sine-Wave Clock Buffer with LDO. datasheet (Rev. C)	25 jul 2012
	Application note	Power Supply Rejection to Noise in Sinusoidal Clock Buffers: CDC3S04 (Rev. A)	21 jun 2010
	Application note	Using the CDC3S04	18 abr 2010
	User guide	Quad Sine-Wave Clock Buffer Evaluation Board	08 mar 2010

Diseño y desarrollo

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CDC3S04EVM — Módulo de evaluación CDC3S04

The CDC3S04 is a four-channel low-power sine-wave clock buffer. It can be used to buffer a single mastern clock to multiple peripherals. The four sine-wave outputs (CLK1–CLK4) are designed for minimal channel-to-channel skew and ultralow additive output jitter. Each output has its own clock (...)

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Modelo de simulación

CDC3S04 IBIS Model (Rev. A)

SLLM072A.ZIP (63 KB) - IBIS Model

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CDC3S04

Búfer de reloj de onda senoidal cuádruple con LDO

CDC3S04

Detalles del producto

Documentación técnica

Diseño y desarrollo

CDC3S04EVM — Módulo de evaluación CDC3S04

CDC3S04 IBIS Model (Rev. A)

CLOCK-TREE-ARCHITECT — Software de programación de diseño de árbol de reloj

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

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