CDCE6214

Name: CDCE6214
Brand: TI
SKU: CDCE6214
Price: 2.1 USD

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Generador de reloj de potencia ultrabaja con un PLL y cuatro salidas diferenciales

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document-pdfAcrobat CDCE6214 Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, Two Inputs, and Internal EEPROM datasheet (Inglés) PDF | HTML

CDCE6214

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Detalles del producto

Function

Clock generator

Number of outputs

4

Output frequency (max) (MHz)

350

Core supply voltage (V)

1.8, 2.5, 3.3

Output supply voltage (V)

1.8, 2.5, 3.3

Input type

LVCMOS, Universal input, XTAL

Output type

HCSL, LVCMOS, LVDS

Operating temperature range (°C)

-40 to 105

Features

I2C, Integrated EEPROM, Pin programmable, Serial interface

Rating

Catalog

Function

Clock generator

Number of outputs

4

Output frequency (max) (MHz)

350

Core supply voltage (V)

1.8, 2.5, 3.3

Output supply voltage (V)

1.8, 2.5, 3.3

Input type

LVCMOS, Universal input, XTAL

Output type

HCSL, LVCMOS, LVDS

Operating temperature range (°C)

-40 to 105

Features

I2C, Integrated EEPROM, Pin programmable, Serial interface

Rating

Catalog

VQFN (RGE)

24

16 mm² 4 x 4

Configurable high performance, low-power, frac-N PLL with RMS jitter with spurs (12 kHz – 20 MHz, F_out > 100 MHz) as:
- Integer mode:
  - Differential output: 350 fs typical, 600 fs maximum
  - LVCMOS output: 1.05 ps typical, 1.5 ps maximum
- Fractional mode:
  - Differential output: 1.7 ps typical, 2.1 ps maximum
  - LVCMOS output: 2.0 ps typical, 4.0 ps maximum
Supports PCIe Gen1/2/3/4 with SSC and Gen 1/2/3/4/5 without SSC
2.335-GHz to 2.625-GHz internal VCO
Typical power consumption: 65 mA for 4-output channel, 23 mA for 1-output channel.
Universal clock input, two reference inputs for redundancy
- Differential AC-coupled or LVCMOS: 10 MHz to 200 MHz
- Crystal: 10 MHz to 50 MHz
Flexible output clock distribution
- 4 channel dividers: Up to 5 unique output frequencies from 24 kHz to 328.125 MHz
- Combination of LVDS-like, LP-HCSL or LVCMOS outputs on OUT0 – OUT4 pins
- Glitchless output divider switching and output channel synchronization
- Individual output enable through GPIO and register
Frequency margining options
- DCO mode: frequency increment/decrement with 10ppb or less step-size
Fully-integrated, configurable loop bandwidth: 100 kHz to 1.6 MHz
Single or mixed supply for level translation: 1.8 V/2.5 V/3.3 V
Configurable GPIOs and flexible configuration options
- I²C-compatible interface: up to 400 kHz
- Integrated EEPROM with two pages and external select pin. In-situ programming allowed.
Supports 100-Ω systems
Low electromagnetic emissions
Small footprint: 24-pin VQFN (4 mm × 4 mm)

Configurable high performance, low-power, frac-N PLL with RMS jitter with spurs (12 kHz – 20 MHz, F_out > 100 MHz) as:
- Integer mode:
  - Differential output: 350 fs typical, 600 fs maximum
  - LVCMOS output: 1.05 ps typical, 1.5 ps maximum
- Fractional mode:
  - Differential output: 1.7 ps typical, 2.1 ps maximum
  - LVCMOS output: 2.0 ps typical, 4.0 ps maximum
Supports PCIe Gen1/2/3/4 with SSC and Gen 1/2/3/4/5 without SSC
2.335-GHz to 2.625-GHz internal VCO
Typical power consumption: 65 mA for 4-output channel, 23 mA for 1-output channel.
Universal clock input, two reference inputs for redundancy
- Differential AC-coupled or LVCMOS: 10 MHz to 200 MHz
- Crystal: 10 MHz to 50 MHz
Flexible output clock distribution
- 4 channel dividers: Up to 5 unique output frequencies from 24 kHz to 328.125 MHz
- Combination of LVDS-like, LP-HCSL or LVCMOS outputs on OUT0 – OUT4 pins
- Glitchless output divider switching and output channel synchronization
- Individual output enable through GPIO and register
Frequency margining options
- DCO mode: frequency increment/decrement with 10ppb or less step-size
Fully-integrated, configurable loop bandwidth: 100 kHz to 1.6 MHz
Single or mixed supply for level translation: 1.8 V/2.5 V/3.3 V
Configurable GPIOs and flexible configuration options
- I²C-compatible interface: up to 400 kHz
- Integrated EEPROM with two pages and external select pin. In-situ programming allowed.
Supports 100-Ω systems
Low electromagnetic emissions
Small footprint: 24-pin VQFN (4 mm × 4 mm)

The CDCE6214 is a four-channel, ultra-low power, medium grade jitter, clock generator that can generate five independent clock outputs selectable between various modes of drivers. The input source could be a single-ended or differential input clock source, or a crystal. The CDCE6214 features a frac-N PLL to synthesize unrelated base frequency from any input frequency. The CDCE6214 can be configured through the I²C interface. In the absence of the serial interface, the GPIO pins can be used in Pin Mode to configure the product into distinctive configurations.

On-chip EEPROM can be used to change the configuration, which is pre-selectable through the pins. The device provides frequency margining options with glitch-free operation to support system design verification tests (DVT) and Ethernet Audio-Video Bridging (eAVB). Fine frequency margining is available on any output channel by steering the fractional feedback divider in DCO mode.

Internal power conditioning provides excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The analog and digital core blocks operate from either a 1.8-V, 2.5-V, or 3.3-V ±5% supply, and output blocks operate from a 1.8-V, 2.5-V, or 3.3-V ±5% supply.

The CDCE6214 enables high-performance clock trees from a single reference at ultra-low power with a small footprint. The factory- and user-programmable EEPROM features make the CDCE6214 an easy-to-use, instant-on clocking device with a low power consumption.

The CDCE6214 is a four-channel, ultra-low power, medium grade jitter, clock generator that can generate five independent clock outputs selectable between various modes of drivers. The input source could be a single-ended or differential input clock source, or a crystal. The CDCE6214 features a frac-N PLL to synthesize unrelated base frequency from any input frequency. The CDCE6214 can be configured through the I²C interface. In the absence of the serial interface, the GPIO pins can be used in Pin Mode to configure the product into distinctive configurations.

On-chip EEPROM can be used to change the configuration, which is pre-selectable through the pins. The device provides frequency margining options with glitch-free operation to support system design verification tests (DVT) and Ethernet Audio-Video Bridging (eAVB). Fine frequency margining is available on any output channel by steering the fractional feedback divider in DCO mode.

Internal power conditioning provides excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The analog and digital core blocks operate from either a 1.8-V, 2.5-V, or 3.3-V ±5% supply, and output blocks operate from a 1.8-V, 2.5-V, or 3.3-V ±5% supply.

The CDCE6214 enables high-performance clock trees from a single reference at ultra-low power with a small footprint. The factory- and user-programmable EEPROM features make the CDCE6214 an easy-to-use, instant-on clocking device with a low power consumption.

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Documentación técnica

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	Tipo	Título		Fecha
*	Data sheet	CDCE6214 Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, Two Inputs, and Internal EEPROM datasheet	PDF \| HTML	02 jul 2020
	Application note	Clocking for PCIe Applications	PDF \| HTML	28 nov 2023
	User guide	CDCE6214-Q1 Registers (Rev. B)		27 nov 2019

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

CDCE6214-Q1EVM — Módulo de evaluación de generador de reloj de 4 salidas diferenciales y 1 salida LVCMOS

The CDCE6214-Q1 evalution module (EVM) is an evaluation platform for the CDCE6214-Q1 ultra-low power clock generator. This
evaluation module provides an USB-based interface to access the I²C bus to communicate with the CDCE6214-Q1. Pin control mode can set the device in a specific operation

Guía del usuario: PDF

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Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.

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Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)

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Encapsulado	Pines	Símbolos CAD, huellas y modelos 3D
VQFN (RGE)	24	Ultra Librarian

Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

CDCE6214

Generador de reloj de potencia ultrabaja con un PLL y cuatro salidas diferenciales

CDCE6214

Detalles del producto

Productos similares que pueden interesarle

Misma funcionalidad con diferente configuración de pines que el dispositivo comparado

Documentación técnica

Diseño y desarrollo

CDCE6214-Q1EVM — Módulo de evaluación de generador de reloj de 4 salidas diferenciales y 1 salida LVCMOS

CLOCK-TREE-ARCHITECT — Software de programación de diseño de árbol de reloj

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

Pedidos y calidad

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Serie de videos

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