LMH1982
Generador de reloj de video multifrecuencia con Genlock
LMH1982
- Two Simultaneous LVDS Output Clocks with
Selectable Frequencies and Hi-Z Capability:- SD Clock: 27 MHz or 67.5 MHz
- HD Clock: 74.25 MHz, 74.25/1.001 MHz,
148.5 MHz or 148.5/1.001 MHz
- Low-Jitter Output Clocks May Be Directly
Connected to an FPGA Serializer to Meet SMPTE
SDI Jitter Specifications - Top of Frame (TOF) Pulse with Programmable
Output Format Timing and Hi-Z Capability - Two reference ports (A and B) With H and V Sync
Inputs - Supports Cross-Locking of Input and Output
Timing - External Loop Filter Allows Control of Loop
Bandwidth, Jitter Transfer, and Lock Time
Characteristics - Free Run or Holdover Operation on Loss of
Reference - User-Defined Free Run Control Voltage Input
- I2C Interface and Control Registers
- 3.3-V and 2.5-V Supplies
The LMH1982 device is a multi-rate video clock generator ideal for use in a wide range of 3-Gbps (3G), high-definition (HD), and standard-definition (SD) video applications, such as video synchronization, serial digital interface (SDI) serializer and deserializer (SerDes), video conversion, video editing, and other broadcast and professional video systems.
The LMH1982 can generate two simultaneous SD and HD clocks and a Top of Frame (TOF) pulse. In genlock mode, the device's phase locked loops (PLLs) can synchronize the output signals to H sync and V sync input signals applied to either of the reference ports. The input reference can have analog timing from Texas Instrument's LMH1981 multi-format video sync separator or digital timing from an SDI deserializer and should conform to the major SD and HD standards. When a loss of reference occurs, the device can default to free run operation where the output timing accuracy will be determined by the external bias on the free run control voltage input.
The LMH1982 can replace discrete PLLs and field-programmable gate array (FPGA) PLLs with multiple voltage controlled crystal oscillators (VCXOs). Only one 27.0000 MHz VCXO and loop filter are externally required for genlock mode. The external loop filter as well as programmable PLL parameters can provide narrow loop bandwidths to minimize jitter transfer. HD clock output jitter as low as 40 ps peak-to-peak can help designers using FPGA SerDes meet stringent SDI output jitter specifications.
The LMH1982 is offered in a space-saving 5 mm × 5 mm 32-pin WQFN package and provides low total power consumption of about 250 mW (typical).
Documentación técnica
| Tipo | Título | Fecha | ||
|---|---|---|---|---|
| * | Data sheet | LMH1982 Multi-Rate Video Clock Generator With Genlock datasheet (Rev. D) | PDF | HTML | 30 sep 2015 |
| Selection guide | Broadcast and Professional Video Interface Solutions (Rev. E) | 05 abr 2017 | ||
| EVM User's guide | AN-1841 LMH1982 Evaluation Board User Guide (Rev. A) | 26 abr 2013 | ||
| Application note | Demonst SMPTE-Compliant SDI Out Jittr Using LMH1982 & Virtx-5 GTP Xmittr (Rev. A) | 26 abr 2013 | ||
| Application note | Triple Rate SDI IP FPGA Resource Utilization on SDXILEVK/AES-EXP-SDI-G Ref Dsgn (Rev. A) | 26 abr 2013 | ||
| More literature | LMH1982 SD/HD Video Clock and Timing Generator with Genlock Capability | 25 ene 2012 | ||
| Design guide | Broadcast Video Owner's Manual | 17 nov 2006 |
Diseño y desarrollo
Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.
PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI
| Encapsulado | Pines | Símbolos CAD, huellas y modelos 3D |
|---|---|---|
| WQFN (RTV) | 32 | Ultra Librarian |
Pedidos y calidad
- RoHS
- REACH
- Marcado del dispositivo
- Acabado de plomo/material de la bola
- Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
- Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
- Contenido del material
- Resumen de calificaciones
- Monitoreo continuo de confiabilidad
- Lugar de fabricación
- Lugar de ensamblaje
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Soporte y capacitación
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