Detalles del producto

2nd harmonic (dBc) 82 3rd harmonic (dBc) 94 Frequency of harmonic distortion measurement (MHz) 100 Acl, min spec gain (V/V) 0.35 Architecture Fully Differential ADC Driver, VGA BW at Acl (MHz) 1100 Gain (max) (dB) 30 Gain (min) (dB) -9 Step size (dB) 1 Type RF VGA Iq per channel (typ) (mA) 105 Number of channels 2 Rating Catalog Operating temperature range (°C) -40 to 85 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.25 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 4.75 Vs (min) (V) 4.75 Vs (max) (V) 5.25
2nd harmonic (dBc) 82 3rd harmonic (dBc) 94 Frequency of harmonic distortion measurement (MHz) 100 Acl, min spec gain (V/V) 0.35 Architecture Fully Differential ADC Driver, VGA BW at Acl (MHz) 1100 Gain (max) (dB) 30 Gain (min) (dB) -9 Step size (dB) 1 Type RF VGA Iq per channel (typ) (mA) 105 Number of channels 2 Rating Catalog Operating temperature range (°C) -40 to 85 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.25 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 4.75 Vs (min) (V) 4.75 Vs (max) (V) 5.25
VQFN (RHA) 40 36 mm² 6 x 6
  • Dual-Channel, Individual SPI™-Controlled DVGA
  • Single 5-V Supply
  • –3-dB Bandwidth: 1.1 GHz (Max Gain)
  • Flat Bandwidth Response: 300 MHz
  • Channel-to-Channel Gain Matching: ±0.05 dB
  • Channel-to-Channel Phase Matching: ±0.1°
  • Gain:
    • 30 dB to –9 dB
    • 1-dB Steps ±0.2 dB
  • Output Third-Order Intercept Point (OIP3):
    • 43 dBm at 300 MHz
    • 51 dBm at 200 MHz
  • Noise Figure (NF):
    • 6.5 dB (Max Gain) at 300 MHz, ZIN = 150 Ω
  • Adjustable Power Consumption:
    • 90 mA to 108 mA per Channel
  • Power-Saving, Power-Down Feature:
    • IQ < 4.5 mA per Channel
    • Power-Down Pin and SPI Programmability
  • Input Return Loss at 300 MHz:
    • 17 dB (RS = 150 Ω)
  • Dual-Channel, Individual SPI™-Controlled DVGA
  • Single 5-V Supply
  • –3-dB Bandwidth: 1.1 GHz (Max Gain)
  • Flat Bandwidth Response: 300 MHz
  • Channel-to-Channel Gain Matching: ±0.05 dB
  • Channel-to-Channel Phase Matching: ±0.1°
  • Gain:
    • 30 dB to –9 dB
    • 1-dB Steps ±0.2 dB
  • Output Third-Order Intercept Point (OIP3):
    • 43 dBm at 300 MHz
    • 51 dBm at 200 MHz
  • Noise Figure (NF):
    • 6.5 dB (Max Gain) at 300 MHz, ZIN = 150 Ω
  • Adjustable Power Consumption:
    • 90 mA to 108 mA per Channel
  • Power-Saving, Power-Down Feature:
    • IQ < 4.5 mA per Channel
    • Power-Down Pin and SPI Programmability
  • Input Return Loss at 300 MHz:
    • 17 dB (RS = 150 Ω)

The LMH2832 is a high-linearity, dual-channel, digital variable-gain amplifier (DVGA) for high-speed signal chain and data-acquisition systems. The LMH2832 is optimized to provide high bandwidth, low distortion, and low noise, thus making the device ideally suited as a dual, 14-bit, analog-to-digital converter (ADC) driver. The device consists of one fixed-gain block and one variable attenuator consisting of a total gain of 30 dB with a maximum attenuation of 39 dB. The gain range is from 30 dB to –9 dB in 1-dB gain steps with a gain accuracy of ±0.2 dB. The input impedance can be easily matched to 50-Ω or 75-Ω systems using a 1:3-Ω or 1:2-Ω ratio balun, respectively. The LMH2832 is designed to drive general-purpose ADCs and also meets the requirements for both data over cable service interface specification (DOCSIS) 3.0 32 quadrature amplitude modulation (QAM) carriers and DOCSIS 3.1 wideband orthogonal frequency-division multiplexing (OFDM) systems. With excellent NF (6.5 dB) and linearity, the LMH2832 is designed to perform to within DOCSIS specifications. The quiescent current in the power-down state is less than 5 mA per channel with the typical current consumption during operation at 105 mA per channel.

The LMH2832 is a high-linearity, dual-channel, digital variable-gain amplifier (DVGA) for high-speed signal chain and data-acquisition systems. The LMH2832 is optimized to provide high bandwidth, low distortion, and low noise, thus making the device ideally suited as a dual, 14-bit, analog-to-digital converter (ADC) driver. The device consists of one fixed-gain block and one variable attenuator consisting of a total gain of 30 dB with a maximum attenuation of 39 dB. The gain range is from 30 dB to –9 dB in 1-dB gain steps with a gain accuracy of ±0.2 dB. The input impedance can be easily matched to 50-Ω or 75-Ω systems using a 1:3-Ω or 1:2-Ω ratio balun, respectively. The LMH2832 is designed to drive general-purpose ADCs and also meets the requirements for both data over cable service interface specification (DOCSIS) 3.0 32 quadrature amplitude modulation (QAM) carriers and DOCSIS 3.1 wideband orthogonal frequency-division multiplexing (OFDM) systems. With excellent NF (6.5 dB) and linearity, the LMH2832 is designed to perform to within DOCSIS specifications. The quiescent current in the power-down state is less than 5 mA per channel with the typical current consumption during operation at 105 mA per channel.

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Documentación técnica

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Tipo Título Fecha
* Data sheet LMH2832 Fully Differential, Dual, 1.1-GHz, Digital Variable-Gain Amplifier datasheet (Rev. A) PDF | HTML 18 jul 2016
E-book The Signal e-book: A compendium of blog posts on op amp design topics 28 mar 2017
EVM User's guide LMH2832EVM-50 Evaluation Module User's Guide 30 jun 2016
EVM User's guide LMH2832EVM-75 Evaluation Module User's Guide 30 jun 2016

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

LMH2832EVM-50 — Módulo de evaluación LMH2832EVM-50

The LMH2832EVM-50 evaluation module (EVM) is used to evaluate the dual LMH2832, digitally-controlled variable gain amplifier (DVGA) in a 40-pin VQFN package. The EVM is used to easily demonstrate the functionality and performance of LMH2832 across all the gain settings in a 50-Ω input (...)
Guía del usuario: PDF
GUI para el módulo de evaluación (EVM)

SLOC338 LMH2832 EVM GUI Setup

Productos y hardware compatibles

Productos y hardware compatibles

Productos
VGA de RF
LMH2832 Amplificador completamente diferencial de ganancia variable digital doble de 1.1 GHz
Modelo de simulación

LMH2832 ADS Model (Rev. A)

SBOJ017A.ZIP (73 KB) - Spice Model
Modelo de simulación

LMH2832 PSpice Model

SBOMBQ4.ZIP (180 KB) - PSpice Model
Modelo de simulación

LMH2832 TINA-TI Reference Design (Rev. A)

SBOMA21A.TSC (261 KB) - TINA-TI Reference Design
Modelo de simulación

LMH2832 TINA-TI Spice Model (Rev. A)

SBOMA22A.ZIP (8 KB) - TINA-TI Spice Model
Diseños de referencia

TIDA-01378 — Diseño de referencia de receptor de banda ancha para aplicaciones DOCSIS 3.1 del cliente al servidor

This reference design consists of an analog front-end (AFE) signal chain for wideband receiver applications using the LMH2832 digitally controlled variable gain amplifier (DVGA) and ADS54J40 analog-to-digital converter (ADC). The design is primarily targeted for upstream DOCSIS 3.1 receiver (...)
Design guide: PDF
Esquema: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
VQFN (RHA) 40 Ultra Librarian

Pedidos y calidad

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  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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