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Microcontroladores (MCU) y procesadores
Microprocesadores y DSP
SoC del procesador de señal digital (DSP) de radar y audio

TMS320C6211B

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DSP de punto fijo C62x de hasta 167 MHz

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TMS320C6211B

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Detalles del producto

CPU 32-/64-bit Frequency (MHz) 167 Rating Catalog Operating temperature range (°C) to
CPU 32-/64-bit Frequency (MHz) 167 Rating Catalog Operating temperature range (°C) to
BGA (ZFN) 256 729 mm² 27 x 27 PBGA (GFN) 256 729 mm² 27 x 27
  • Excellent Price/Performance Digital Signal Processors (DSPs): TMS320C62x™ (TMS320C6211 and TMS320C6211B)
    • Eight 32-Bit Instructions/Cycle
    • C6211, C6211B, C6711, and C6711B are Pin-Compatible
    • 150-, 167-MHz Clock Rates
    • 6.7-, 6-ns Instruction Cycle Time
    • 1200, 1333 MIPS
    • Extended Temperature Device (C6211B)
  • VelociTI™ Advanced Very Long Instruction Word (VLIW) C62x™ DSP Core (C6211/11B)
    • Eight Highly Independent Functional Units:
      • Six ALUs (32-/40-Bit)
      • Two 16-Bit Multipliers (32-Bit Results)
    • Load-Store Architecture With 32 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit-Counting
    • Normalization
  • L1/L2 Memory Architecture
    • 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
    • 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
  • Device Configuration
    • Boot Mode: HPI, 8-, 16-, and 32-Bit ROM Boot
    • Endianness: Little Endian, Big Endian
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories: SRAM and EPROM
    • Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
    • 512M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
  • 16-Bit Host-Port Interface (HPI)
    • Access to Entire Memory Map
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • ST-Bus-Switching Compatible
    • Up to 256 Channels Each
    • AC97-Compatible
    • Serial-Peripheral-Interface (SPI) Compatible (Motorola™)
  • Two 32-Bit General-Purpose Timers
  • Flexible Phase-Locked-Loop (PLL) Clock Generator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 256-Pin Ball Grid Array (BGA) Package (GFN and ZFN Suffixes)
  • 0.18-µm/5-Level Metal Process
    • CMOS Technology
  • 3.3-V I/Os, 1.8-V Internal

TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
  • Excellent Price/Performance Digital Signal Processors (DSPs): TMS320C62x™ (TMS320C6211 and TMS320C6211B)
    • Eight 32-Bit Instructions/Cycle
    • C6211, C6211B, C6711, and C6711B are Pin-Compatible
    • 150-, 167-MHz Clock Rates
    • 6.7-, 6-ns Instruction Cycle Time
    • 1200, 1333 MIPS
    • Extended Temperature Device (C6211B)
  • VelociTI™ Advanced Very Long Instruction Word (VLIW) C62x™ DSP Core (C6211/11B)
    • Eight Highly Independent Functional Units:
      • Six ALUs (32-/40-Bit)
      • Two 16-Bit Multipliers (32-Bit Results)
    • Load-Store Architecture With 32 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit-Counting
    • Normalization
  • L1/L2 Memory Architecture
    • 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
    • 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
  • Device Configuration
    • Boot Mode: HPI, 8-, 16-, and 32-Bit ROM Boot
    • Endianness: Little Endian, Big Endian
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories: SRAM and EPROM
    • Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
    • 512M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
  • 16-Bit Host-Port Interface (HPI)
    • Access to Entire Memory Map
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • ST-Bus-Switching Compatible
    • Up to 256 Channels Each
    • AC97-Compatible
    • Serial-Peripheral-Interface (SPI) Compatible (Motorola™)
  • Two 32-Bit General-Purpose Timers
  • Flexible Phase-Locked-Loop (PLL) Clock Generator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 256-Pin Ball Grid Array (BGA) Package (GFN and ZFN Suffixes)
  • 0.18-µm/5-Level Metal Process
    • CMOS Technology
  • 3.3-V I/Os, 1.8-V Internal

TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

The TMS320C62x™ DSPs (including the TMS320C6211/C6211B devices) compose one of the fixed-point DSP families in the TMS320C6000™ DSP platform. The TMS320C6211 (C6211) and TMS320C6211B (C6211B) devices are based on the high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.

With performance of up to 1333 million instructions per second (MIPS) at a clock rate of 167 MHz, the C6211/C6211B device offers cost-effective solutions to high-performance DSP programming challenges. The C6211/C6211B DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6211/C6211B can produce two multiply-accumulates (MACs) per cycle for a total of 333 million MACs per second (MMACS). The C6211/C6211B DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6211/C6211B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.

The C6211/C6211B has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The TMS320C62x™ DSPs (including the TMS320C6211/C6211B devices) compose one of the fixed-point DSP families in the TMS320C6000™ DSP platform. The TMS320C6211 (C6211) and TMS320C6211B (C6211B) devices are based on the high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.

With performance of up to 1333 million instructions per second (MIPS) at a clock rate of 167 MHz, the C6211/C6211B device offers cost-effective solutions to high-performance DSP programming challenges. The C6211/C6211B DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6211/C6211B can produce two multiply-accumulates (MACs) per cycle for a total of 333 million MACs per second (MMACS). The C6211/C6211B DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6211/C6211B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.

The C6211/C6211B has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.
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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Fecha
* Data sheet TMS320C6211, TMS320C6211B Fixed-Point Digital Signal Processors datasheet (Rev. L) 09 jun 2004
* Errata TMS320C6211/TMS320C6211B DSPs Silicon Errata (Revs 1.0, 1.1, 2.1, 2.2, 3.0, 3.1) (Rev. L) 28 may 2004
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 19 may 2021
Application note Introduction to TMS320C6000 DSP Optimization 06 oct 2011
User guide TMS320C62x DSP CPU and Instruction Set Reference Guide (Rev. A) 20 may 2010
User guide TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) 02 jul 2009
Application note TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E) 04 sep 2007
Application note Thermal Considerations for the DM64xx, DM64x, and C6000 Devices 20 may 2007
User guide TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E) 11 abr 2007
User guide TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G) 14 dic 2006
User guide TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C) 15 nov 2006
User guide TMS320C6000 CPU and Instruction Set Reference Guide (Rev. G) 11 jul 2006
User guide TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C) 01 ene 2006
Application note Migrating from TMS320C6211B/C6711/C6711B and C6713 to TMS320C6713B (Rev. H) 11 nov 2005
Application note Migrating From TMS320C6211B/C6711/C6711B/C6711C to TMS320C6711D (Rev. H) 10 nov 2005
User guide TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C) 01 mar 2005
User guide TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B) 25 ene 2005
User guide TMS320C621x/C671x DSP Two Level Internal Memory Reference Guide (Rev. B) 08 jun 2004
Application note TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D) 26 abr 2004
Application note TMS320C6000 Board Design: Considerations for Debug (Rev. C) 21 abr 2004
Application note TMS320C6000 McBSP Initialization (Rev. C) 08 mar 2004
Application note TMS320C621x/671x EDMA Performance Data 05 mar 2004
Application note TMS320C621x/TMS320C671x EDMA Architecture 05 mar 2004
User guide TMS320C6000 DSP Designing for JTAG Emulation Reference Guide 31 jul 2003
User guide TMS320C6000 DSP Cache User's Guide (Rev. A) 05 may 2003
Application note Migrating from TMS320C6211 to TMS320C6211B 28 abr 2003
Application note Using IBIS Models for Timing Analysis (Rev. A) 15 abr 2003
Application note Extended Precision Radix-4 Fast Fourier Transform Implemented on the TMS320C62x 23 nov 2002
Application note TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B) 04 jun 2002
Application note TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C) 17 abr 2002
Application note TMS320C6000 DMA Example Applications (Rev. A) 10 abr 2002
Application note TMS320C6000 Board Design for JTAG (Rev. C) 02 abr 2002
Application note TMS320C6000 EMIF to External Flash Memory (Rev. A) 13 feb 2002
Application note Using a TMS320C6000 McBSP for Data Packing (Rev. A) 31 oct 2001
Application note TMS320C6000 Enhanced DMA: Example Applications (Rev. A) 24 oct 2001
Application note Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A) 30 sep 2001
Application note TMS320C6000 Host Port to MC68360 Interface (Rev. A) 30 sep 2001
Application note TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A) 31 ago 2001
Application note TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A) 31 ago 2001
Application note Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A) 31 ago 2001
Application note TMS320C6000 System Clock Circuit Example (Rev. A) 15 ago 2001
Application note TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A) 23 jul 2001
Application note TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A) 10 jul 2001
Application note TMS320C6000 McBSP: Interface to SPI ROM (Rev. C) 30 jun 2001
Application note TMS320C6000 Host Port to MPC860 Interface (Rev. A) 21 jun 2001
Application note TMS320C6000 McBSP: IOM-2 Interface (Rev. A) 21 may 2001
Application note ETSI Math Operations in C for the TMS320C62x (Rev. A) 13 nov 2000
Application note TMS320C621x/C671x EDMA Queue Management Guidelines 07 nov 2000
Application note Optimizing JPEG on the TMS320C6211 2-Level Cache DSP 13 sep 2000
Application note Circular Buffering on TMS320C6000 (Rev. A) 12 sep 2000
Application note TMS320C6000 McBSP as a TDM Highway (Rev. A) 11 sep 2000
Application note MPEG-2 Video Decoder: TMS320C62x (TM) DSP Implementation 29 feb 2000
Application note TMS320C6000 u-Law and a-Law Companding with Software or the McBSP 02 feb 2000
Application note General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point 31 ene 2000
Application note G.723.1 Dual Rate Speech Coder: Multichannel TMS320C62x Implementation (Rev. B) 04 ene 2000
Application note G.729/A Speech Coder: Multichannel TMS320C62x Implementation (Rev. B) 04 ene 2000
Application note GSM Enhanced Full Rate Speech Coder: Multichannel TMS320C62x Implementation (Rev. B) 04 ene 2000
Application note IS-127 Enhanced Var Rate Speech Coder:Multichannel TMS320C62x Implementation (Rev. B) 04 ene 2000
Application note TMS320C6000 C Compiler: C Implementation of Intrinsics 07 dic 1999
Application note TMS320C6000 McBSP: I2S Interface 08 sep 1999
Application note On the Implementation of MPEG-4 Motion Compensation Using the TMS320C62x 29 jul 1999

Diseño y desarrollo

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Sonda de depuración

LB-3P-TRACE32-DSP — Sistema de depuración y seguimiento Lauterbach TRACE32 para procesadores de señales digitales (DSP)

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

Desde: Lauterbach GmbH
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AEC-AER — Acoustic echo cancellation/removal for TI C64x+, C674x, C55x and Cortex®-A8 processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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C64X-DSPLIB — Download TMS320C64x DSP Library

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

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C67X-DSPLIB — Download TMS320C67x DSP Library

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

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FAXLIB — FAX library (FAXLIB) for C66x, C64x+ and C55x processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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SPRC122 — C62x/C64x Fast Run-Time Support Library

The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)

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VOLIB — Voice library (VoLIB) for C66x, C64x+ and C55x processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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Modelo de simulación

C6211B GFN Rev 3.0 BSDL Model (Rev. B)

SPRM036B.ZIP (5 KB) - BSDL Model
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