Detalles del producto

DSP type 1 C64x DSP (max) (MHz) 594 CPU 32-/64-bit Operating system DSP/BIOS, Integrity, Linux, Neutrino, PrOS, Windows Embedded CE Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) to
DSP type 1 C64x DSP (max) (MHz) 594 CPU 32-/64-bit Operating system DSP/BIOS, Integrity, Linux, Neutrino, PrOS, Windows Embedded CE Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) to
NFBGA (ZWT) 361 256 mm² 16 x 16
  • Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
  • High-Performance Digital Media SoC
    • 594-MHz C64x+™ Clock Rate
    • 297-MHz ARM926EJ-S™ Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 4752 C64x+ MIPS
    • Fully Software-Compatible With C64x /ARM9™
  • Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
    • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 32K-Byte L1P Program RAM/Cache (Direct Mapped)
    • 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
    • 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • ARM926EJ-S (MPU) Core
    • Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM® Jazelle® Technology
    • EmbeddedICE-RT™ Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 16K-Byte RAM
    • 16K-Byte ROM
  • Emulation Trace Buffer™ (ETB11™) With 4-KB Memory for ARM9 Debug
  • Endianness: Little Endian for ARM and DSP
  • Video Processing Subsystem
    • Resize Engine Provides:
      • Resize Images From 1/4x to 4x
      • Separate Horizontal and Vertical Control
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • 4 - 54 MHz DACs for a Combination of
        • Composite NTSC/PAL Video
        • Luma/Chroma Separate Video (S-video)
        • Component (YPbPr or RGB) Video (Progressive)
      • Digital Output
        • 8-/16-Bit YUV or up to 24-Bit RGB
        • HD Resolution
        • Up to 2 Video Windows
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8V I/O)
    • Asynchronous16-Bit-Wide EMIF (EMIFA) With 128M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-/16-Bit-Wide Data)
        • NAND (8-/16-Bit-Wide Data)
  • Flash Card Interfaces
    • Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
    • CompactFlash Controller With True IDE Mode
    • SmartMedia
  • Enhanced Direct-Memory-Access (EDMA3) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Three UARTs (One with RTS and CTS Flow Control)
  • One Serial Port Interface (SPI) with Two Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Audio Serial Port (ASP)
    • I2S
    • AC97 Audio Codec Interface
    • Standard Voice Codec Interface (AIC12)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
  • VLYNQ™ Interface (FPGA Interface)
  • Host-Port Interface (HPI) with 16-Bit Multiplexed Address/Data
  • USB Port With Integrated 2.0 PHY
    • USB 2.0 High-/Full-Speed (480 Mbps) Client
    • USB 2.0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device)
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART
  • ATA/ATAPI I/F (ATA/ATAPI-6 Specification)
  • Individual Power-Saving Modes for ARM/DSP
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • 361-Pin Pb-Free BGA Package (ZWT Suffix), 0.8-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal
  • Applications:
    • Digital Media
    • Networked Media Encode/Decode
    • Video Imaging

All trademarks are the property of their respective owners.

  • Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
  • High-Performance Digital Media SoC
    • 594-MHz C64x+™ Clock Rate
    • 297-MHz ARM926EJ-S™ Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 4752 C64x+ MIPS
    • Fully Software-Compatible With C64x /ARM9™
  • Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
    • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 32K-Byte L1P Program RAM/Cache (Direct Mapped)
    • 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
    • 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • ARM926EJ-S (MPU) Core
    • Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM® Jazelle® Technology
    • EmbeddedICE-RT™ Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 16K-Byte RAM
    • 16K-Byte ROM
  • Emulation Trace Buffer™ (ETB11™) With 4-KB Memory for ARM9 Debug
  • Endianness: Little Endian for ARM and DSP
  • Video Processing Subsystem
    • Resize Engine Provides:
      • Resize Images From 1/4x to 4x
      • Separate Horizontal and Vertical Control
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • 4 - 54 MHz DACs for a Combination of
        • Composite NTSC/PAL Video
        • Luma/Chroma Separate Video (S-video)
        • Component (YPbPr or RGB) Video (Progressive)
      • Digital Output
        • 8-/16-Bit YUV or up to 24-Bit RGB
        • HD Resolution
        • Up to 2 Video Windows
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8V I/O)
    • Asynchronous16-Bit-Wide EMIF (EMIFA) With 128M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-/16-Bit-Wide Data)
        • NAND (8-/16-Bit-Wide Data)
  • Flash Card Interfaces
    • Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
    • CompactFlash Controller With True IDE Mode
    • SmartMedia
  • Enhanced Direct-Memory-Access (EDMA3) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Three UARTs (One with RTS and CTS Flow Control)
  • One Serial Port Interface (SPI) with Two Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Audio Serial Port (ASP)
    • I2S
    • AC97 Audio Codec Interface
    • Standard Voice Codec Interface (AIC12)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
  • VLYNQ™ Interface (FPGA Interface)
  • Host-Port Interface (HPI) with 16-Bit Multiplexed Address/Data
  • USB Port With Integrated 2.0 PHY
    • USB 2.0 High-/Full-Speed (480 Mbps) Client
    • USB 2.0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device)
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART
  • ATA/ATAPI I/F (ATA/ATAPI-6 Specification)
  • Individual Power-Saving Modes for ARM/DSP
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • 361-Pin Pb-Free BGA Package (ZWT Suffix), 0.8-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal
  • Applications:
    • Digital Media
    • Networked Media Encode/Decode
    • Video Imaging

All trademarks are the property of their respective owners.

The TMS320DM6443 (also referenced as DM6443) leverages TI's Davinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices.

The DM6443 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the DM6443 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+™ DSP core and an ARM926EJ-S MPU core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core incorporates:

  • A coprocessor 15 (CP15) and protection module
  • Data and program Memory Management Units (MMUs) with table look-aside buffers.
  • Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+ DSP with added functionality and an expanded instruction set.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4752 million instructions per second (MIPS) at a clock rate of 594 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units&151;two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2376 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4752 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6443 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6443 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: 1 configurable video port; a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6443 includes a Video Processing Sub-System (VPSS) that has a configurable Resizer and Video Processing Back-End (VPBE) output used for display.

The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM644X MPU core processor and the network. The DM6443 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the MPU, the DIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the MPU, allowing the MPU to poll the link status of the device without continuously performing costly MDIO accesses.

The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6443 to easily control peripheral devices and/or communicate with host processors. The DM6443 also provides multimedia card support, MMC/SD, with SDIO support.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The DM6443 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

The TMS320DM6443 (also referenced as DM6443) leverages TI's Davinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices.

The DM6443 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the DM6443 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+™ DSP core and an ARM926EJ-S MPU core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core incorporates:

  • A coprocessor 15 (CP15) and protection module
  • Data and program Memory Management Units (MMUs) with table look-aside buffers.
  • Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+ DSP with added functionality and an expanded instruction set.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4752 million instructions per second (MIPS) at a clock rate of 594 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units&151;two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2376 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4752 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6443 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6443 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: 1 configurable video port; a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6443 includes a Video Processing Sub-System (VPSS) that has a configurable Resizer and Video Processing Back-End (VPBE) output used for display.

The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM644X MPU core processor and the network. The DM6443 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the MPU, the DIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the MPU, allowing the MPU to poll the link status of the device without continuously performing costly MDIO accesses.

The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6443 to easily control peripheral devices and/or communicate with host processors. The DM6443 also provides multimedia card support, MMC/SD, with SDIO support.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The DM6443 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

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Tipo Título Fecha
* Data sheet TMS320DM6443 Digital Media System-on-Chip datasheet (Rev. G) 30 ago 2010
* Errata TMS320DM6443 Digital Media SoC Silicon Errata (Revs 2.3, 2.1, 1.3, 1.2, 1.1) (Rev. N) 12 ago 2010
Application note High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 24 feb 2023
User guide TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W) 21 ago 2012
User guide TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U) 21 ago 2012
User guide Emulation and Trace Headers Technical Reference Manual (Rev. I) 09 ago 2012
Application note Introduction to TMS320C6000 DSP Optimization 06 oct 2011
User guide TMS320DM644x DMSoC 64-bit Timer User's Guide 01 ago 2011
User guide TMS320C6000 Programmer's Guide (Rev. K) 11 jul 2011
User guide TMS320DM644x DMSoC Inter-Integrated Circuit (I2C) Peripheral User's Guide (Rev. F) 25 mar 2011
User guide TMS320DM644x DMSoC Video Processing Back End (VPBE) User's Guide (Rev. D) 27 ene 2011
User guide TMS320DM644x DMSoC DDR2 Memory Controller User's Guide (Rev. E) 12 ene 2011
User guide TMS320DM644x DMSoC EMAC/MDIO Module User's Guide (Rev. B) 23 dic 2010
User guide TMS320DM644x DMSoC Video Processing Front End (VPFE) User's Guide (Rev. H) 25 ago 2010
User guide TMS320DM644x DMSoC General-Purpose Input/Output (GPIO) User's Guide (Rev. A) 19 ago 2010
Application note TMS320DM6446/3 Power Consumption Summary (Rev. B) 16 ago 2010
User guide TMS320DM644x DMSoC Pulse-Width Modulator (PWM) User's Guide (Rev. A) 06 ago 2010
User guide TMS320C64x+ DSP Megamodule Reference Guide (Rev. K) 03 ago 2010
User guide TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 30 jul 2010
User guide TMS320DM644x DMSoC ARM Subsystem Reference Guide (Rev. C) 21 jul 2010
Application note Migrating From TMS320DM644x v.2.1 ROM Bootloader to 2.3 Version 20 jul 2010
User guide TMS320DM644x DMSoC Universal Serial Bus (USB) Controller User's Guide (Rev. G) 02 jun 2010
User guide TMS320C6000 Assembly Language Tools v 7.0 User's Guide (Rev. S) 18 mar 2010
User guide TMS320C6000 Optimizing Compiler v 7.0 User's Guide (Rev. Q) 18 mar 2010
Application note USB Compliance Checklist (Rev. A) 10 mar 2010
Application note Booting and Flashing via the DaVinci TMS320DM644x Serial Interface (Rev. A) 10 sep 2009
Application note LSP 2.10 DaVinci Linux Drivers (Rev. A) 08 jul 2009
Application note Common Object File Format (COFF) 15 abr 2009
User guide TMS320DM644x DMSoC Asynchronous External Memory Interface (EMIF) User's Guide (Rev. C) 24 feb 2009
User guide TMS320DM644x DMSoC Host Port Interface (HPI) User's Guide (Rev. B) 22 feb 2009
User guide TMS320C64x+ DSP Cache User's Guide (Rev. B) 11 feb 2009
Application note Booting DaVinci EVM from NAND Flash (Rev. A) 15 dic 2008
Application note 5 VIN solution using DCDC Controllers, a LDO, and a Digitally Prog. Sequencer 24 nov 2008
More literature DaVinci Technology Overview Brochure (Rev. B) 27 sep 2008
Application note Migrating from EDMA v2.0 to EDMA v3.0 TMS320C64X DSP (Rev. A) 21 ago 2008
Application note Understanding the Davinci Preview Engine (Rev. A) 23 jul 2008
Application note Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) 17 jul 2008
Application note Understanding the Davinci Resizer (Rev. B) 17 jul 2008
Application note Implementing the DDR2 PCB Layout on the TMS320DM644x DMSoC (Rev. G) 16 jun 2008
Application note Building a Small Embedded Linux Kernel Example (Rev. A) 27 may 2008
User guide TMS320DM644x DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card Controller UG (Rev. D) 27 may 2008
User guide TMS320C6000 Assembly Language Tools v 6.1 User's Guide (Rev. Q) 15 may 2008
User guide TMS320C6000 Optimizing Compiler v 6.1 User's Guide (Rev. O) 15 may 2008
User guide TMS320C64x+ DSP Image/Video Processing Library (v2.0) Programmer's Reference (Rev. A) 05 may 2008
Application note TMS320DM644x Thermal Considerations (Rev. A) 23 abr 2008
Application note TMS320DM6441 Power Consumption Summary Application Report 08 abr 2008
User guide TMS320DM644x DMSoC Universal Asynchronous Receiver/Transmitter (UART) UG (Rev. A) 08 abr 2008
User guide TMS320C64x+ DSP Little-Endian Library Programmer's Reference (Rev. B) 06 mar 2008
User guide TMS320DM644x DMSoC Enhanced Direct Memory Access (EDMA) Controller User's Guide (Rev. D) 25 feb 2008
User guide TMS320DM644x DMSoC VLYNQ Port User's Guide (Rev. A) 20 sep 2007
User guide TMS320DM644x DMSoC Audio Serial Port (ASP) User's Guide (Rev. B) 17 sep 2007
Application note Running Demo via ddd on the DVEVM 30 jul 2007
Application note Using Static IP Between Linux Host and the DVEVM 30 jul 2007
Application note Compact Flash (CF) Support on the DVEVM 25 jul 2007
Application note Host USB Support on the DVEVM 20 jul 2007
Application note Decode Demo for the DaVinci DVEVM/DVSDK 1.2 (Rev. A) 27 jun 2007
Application note Digital Video Using DaVinci SoC 27 jun 2007
Application note Encode Demo for the DaVinci DVEVM/DVSDK 1.2 (Rev. A) 27 jun 2007
Application note EncodeDecode Demo for the DaVinci DVEVM/DVSDK 1.2 (Rev. A) 27 jun 2007
User guide TMS320DM644x DMSoC Peripherals Overview Reference Guide (Rev. C) 18 abr 2007
Product overview TMS320C6000 DSP TCP/IP Stack Software (Rev. C) 04 abr 2007
EVM User's guide TMS320DM644x DVEVM Windows CE v5.0 BSP Codec Engine User’s Guide 23 mar 2007
EVM User's guide TMS320DM644x DVEVM Windows CE v5.0 Codec Engine Binary User's Guide 23 mar 2007
Product overview DaVinci Technology - Digital Video Innovation Product Bulletin (Rev. D) 13 feb 2007
More literature Overview of DaVinci™ TMS320DM644x Digital Media Portfolio (Rev. B) 13 feb 2007
User guide TMS320DM644x DMSoC Serial Peripheral Interface (SPI) User's Guide (Rev. A) 07 feb 2007
Application note Basic Application Loading over the Serial Interface for the DaVinci TMS320DM644x 21 dic 2006
Product overview Portable Media Player Based on DaVinci Technology 14 nov 2006
Product overview Universal IP Player Solution from ATEME 02 nov 2006
Application note DaVinci System Level Benchmarking Measurements 28 sep 2006
Product overview DaVinci Benchmarks Product Bulletin (Rev. A) 12 sep 2006
Application note Fast Development with DaVinci On Screen Display (OSD) 06 jul 2006
User guide TMS320C64x+ DSP Big-Endian Library Programmer's Reference 10 mar 2006
User guide TMS320C64x+ Image/Video Processing Library Programmer's Reference 10 mar 2006
Application note Migrating from EDMA v2.0 to EDMA v3.0 for TMS320DM644X DMSoC 03 dic 2005
User guide TMS320DM644x DMSoC ATA Controller User's Guide 03 dic 2005
User guide TMS320DM644x DMSoC DSP Subsystem Reference Guide 03 dic 2005
Application note Migrating from TMS320C64x to TMS320C64x+ (Rev. A) 20 oct 2005

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Sonda de depuración

TMDSADP — Adaptadores emuladores JTAG con cierre adaptable

TMDSADP1420 adapter – used for connecting TI and 3rd party XDS510 and XDS560-class emulators with a 14 pin native connector to the TMDXEVM6446 or customer boards with a compact (CTI) 20-pin header. The adapter improves signal integrity, translates voltages, and can optionally provide adaptive (...)

Guía del usuario: PDF
Sonda de depuración

TMDSEMU200-U — Sonda de depuración XDS200 USB

El XDS200 es una sonda de depuración (emulador) que se utiliza para depurar dispositivos integrados de TI. El XDS200 presenta un equilibrio de bajo costo con buen rendimiento en comparación con el XDS110 de bajo costo y el XDS560v2 de alto rendimiento. Es compatible con una amplia (...)

Sonda de depuración

TMDSEMU560V2STM-U — Sonda de depuración USB de seguimiento del sistema XDS560v2

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Sonda de depuración

TMDSEMU560V2STM-UE — Sonda de depuración USB y ethernet de seguimiento del sistema XDS560v2

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Kit de desarrollo de software (SDK)

LINUXDVSDK-DV — Kits de desarrollo de software de video digital (DVSDK) v2x/v3x: procesadores de medios digitales Da

Effective Oct 2010 - Linux DVSDK v4 has been released. For DaVinci™ devices not listed above, search TI.com for your device part number; This product page will have a link to your current DVSDK.

The Linux™ Digital Video Software Development Kits (DVSDKs) enable DaVinci system integrators to (...)

Software de aplicación y estructura

TMDMFP — Productos de marco multimedia (MFP): motor de códec, componentes de marco y XDAIS

Multimedia Framework Products (MFP)

A major advantage of programmable signal processors over fixed-function devices is their ability to accelerate multiple multimedia functions and provide flexible environments to enable user customization. However, sharing scarce embedded hardware resources between (...)

Guía del usuario: PDF
Controlador o biblioteca

SPRC122 C62x/C64x Fast Run-Time Support Library

The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)

Productos y hardware compatibles

Productos y hardware compatibles

Productos
Procesadores digitales de señales (DSP)
SM320C6201-EP DSP de punto fijo C6201 de producto mejorado SM320C6455-EP DSP de punto fijo C6455 de producto mejorado SMJ320C6201B Procesador de señal digital de punto fijo, de calidad militar SMJ320C6203 DSP de punto fijo de calidad militar C62x: encapsulado cerámico TMS320C6202B DSP de punto fijo C62x de hasta 300 MHz y 384 KB TMS320C6203B DSP de punto fijo C62x de hasta 300 MHz y 896 KB TMS320C6204 Procesador de señal digital de punto fijo TMS320C6205 Procesador de señal digital de punto fijo TMS320C6211B DSP de punto fijo C62x de hasta 167 MHz TMS320C6412 DSP de punto fijo C64x de hasta 720 MHz, con McBSP, McASP, I2cC y Ethernet TMS320C6414 DSP de punto fijo C64x de hasta 720 MHz, McBSP TMS320C6414T DSP de punto fijo C64x de hasta 1 GHz y McBSP TMS320C6415 DSP de punto fijo C64x de hasta 720 MHz, con McBSP y PCI TMS320C6415T DSP de punto fijo C64x de hasta 850 MHz, con McBSP y PCI TMS320C6416 DSP de punto fijo C64x de hasta 720 MHz, con McBSP, PCI y VCP/TCP TMS320C6416T DSP de punto fijo C64x de hasta 850 MHz, con McBSP, PCI y VCP/TCP TMS320C6421 DSP de punto fijo C64x+ de hasta 600 MHz, EMIFA de 8 bits, DDR2 de 16 bits y SDRAM TMS320C6421Q DSP de punto fijo C64x+ de hasta 600 MHz, EMIFA de 8 bits y DDR2 de 16 bits TMS320C6424 DSP de punto fijo C64x+ de hasta 600 MHz, EMIFA de 16/8 bits, DDR2 de 32/16 bits y SDRAM TMS320C6424Q DSP de punto fijo C64x+ de hasta 600 MHz, EMIFA de 16/8 bits y DDR2 de 32/16 bits TMS320C6452 DSP de punto fijo C64x+ de hasta 900 MHz, con Ethernet de 1 Gbps TMS320C6454 DSP de punto fijo C64x+ de hasta 1 GHz, con EMIFA de 64 bits, DDR2 de 32/16 bits y Ethernet de 1 Gbp TMS320C6455 Procesador de señal digital (DSP) de punto fijo C64x+ de hasta 1.2 GHz, interfaz de memoria externa TMS320C6457 Procesador de señal digital de infraestructura de comunicaciones TMS320C6474 Procesador de señal digital multinúcleo TMS320DM640 Procesador de señal digital de punto fijo de imágenes y video TMS320DM641 Procesador de señal digital de punto fijo de imágenes y video TMS320DM642 Procesador de señal digital de punto fijo de imágenes y video TMS320DM642Q Procesador de señal digital de punto fijo de imágenes y video TMS320DM6431 Procesador de medios digitales TMS320DM6431Q Procesador de medios digitales de hasta 2,400 MIPS y velocidad de reloj de 300 MHz TMS320DM6433 Procesador de medios digitales TMS320DM6435 Procesador de medios digitales TMS320DM6435Q Procesador de medios digitales de hasta 4.800 MIPS y velocidad de reloj de 600 MHz, 1 McASP y 1 McBS TMS320DM6437 Procesador de medios digitales TMS320DM6437Q Procesador de medios digitales de hasta 4800 MIPS y velocidad de reloj de 600 MHz con 1 McASP y 2 Mc TMS320DM6441 Sistema en chip de medios digitales DaVinci TMS320DM6443 Sistema en chip de medios digitales DaVinci TMS320DM6446 Sistema en chip de medios digitales DaVinci
Controlador o biblioteca

TELECOMLIB — Bibliotecas de telecomunicaciones y medios: FAXLIB, VoLIB y AEC/AER para procesadores TMS320C64x+ y

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
Códec de software

C64XPLUSCODECS — CÓDECS: video y voz, dispositivos basados en C64x+ (OMAP35x, C645x, C647x, DM646, DM644x, DM643x)

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes are on (...)
Códec de software

DM644XCODECS Codecs for DM644x - Software and Documentation

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio, video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

Productos y hardware compatibles

Productos y hardware compatibles

Productos
Procesadores digitales de señales (DSP)
SM320DM6446-HIREL Procesador DM6446 de medios digitales de productos de alta confiabilidad TMS320DM6441 Sistema en chip de medios digitales DaVinci TMS320DM6443 Sistema en chip de medios digitales DaVinci TMS320DM6446 Sistema en chip de medios digitales DaVinci
Opciones de descarga
Códec de software

TMDXDAISXDM — Estándar de algoritmo eXpressDSP: kit de desarrollo xDAIS y xDM

xDAIS and xDM

The eXpressDSP™ Algorithm Interoperability Standard (xDAIS) and the eXpressDSP Digital Media (xDM) standard fully leverage the ability of DSPs to perform a wide range of multimedia functions on a single device. eXpressDSP compliance is achieved by adhering to these standards. To (...)

Guía del usuario: PDF
Modelo de simulación

DM6443 ZWT BSDL Model

SPRM204.ZIP (10 KB) - BSDL Model
Modelo de simulación

DM6443 ZWT BSDL version 2.1 Model (Rev. A)

SPRM326A.ZIP (8 KB) - BSDL Model
Modelo de simulación

DM6443 ZWT IBIS Model

SPRM199.ZIP (112 KB) - IBIS Model
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
NFBGA (ZWT) 361 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI. ​​​​​​​​​​​​​​

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