홈 클록 및 타이밍 클록 버퍼
홈
클록 및 타이밍
클록 버퍼

CDC111

마지막 구매

3.3V LVPECL 차동 클록 드라이버

지금 주문
데이터 시트

CDC111

마지막 구매
데이터 시트 지금 주문

제품 상세 정보

Function Differential Output frequency (max) (MHz) 500 Number of outputs 9 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 50 Operating temperature range (°C) 0 to 70 Rating Catalog Output type LVPECL Input type LVPECL
Function Differential Output frequency (max) (MHz) 500 Number of outputs 9 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 50 Operating temperature range (°C) 0 to 70 Rating Catalog Output type LVPECL Input type LVPECL
PLCC (FN) 28 155.0025 mm² 12.45 x 12.45
  • Low-Output Skew for Clock-Distribution Applications
  • Differential Low-Voltage Pseudo-ECL (LVPECL)-Compatible Inputs and Outputs
  • Distributes Differential Clock Inputs to Nine Differential Clock Outputs
  • Output Reference Voltage, VREF, Allows Distribution From a Single-Ended Clock Input
  • Single-Ended LVPECL-Compatible Output Enable
  • Packaged in Plastic Chip Carrier
  • Low-Output Skew for Clock-Distribution Applications
  • Differential Low-Voltage Pseudo-ECL (LVPECL)-Compatible Inputs and Outputs
  • Distributes Differential Clock Inputs to Nine Differential Clock Outputs
  • Output Reference Voltage, VREF, Allows Distribution From a Single-Ended Clock Input
  • Single-Ended LVPECL-Compatible Output Enable
  • Packaged in Plastic Chip Carrier

The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, CLKIN\) to nine pairs of differential clock (Y, Y\) outputs with minimum skew for clock distribution. It is specifically designed for driving 50- transmission lines.

When the output-enable (OE\) is low, the nine differential outputs switch at the same frequency as the differential clock inputs. When OE\ is high, the nine differential outputs are in static states (Y outputs are in the low state, Y\ outputs are in the high state).

The VREF output can be strapped to the CLKIN\ input for a single-ended CLKIN input.

The CDC111 is characterized for operation from 0°C to 70°C.

The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, CLKIN\) to nine pairs of differential clock (Y, Y\) outputs with minimum skew for clock distribution. It is specifically designed for driving 50- transmission lines.

When the output-enable (OE\) is low, the nine differential outputs switch at the same frequency as the differential clock inputs. When OE\ is high, the nine differential outputs are in static states (Y outputs are in the low state, Y\ outputs are in the high state).

The VREF output can be strapped to the CLKIN\ input for a single-ended CLKIN input.

The CDC111 is characterized for operation from 0°C to 70°C.
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* Data sheet 1-Line To 9-Line Differential LVPECL Clock Driver datasheet (Rev. G) 1999/08/28

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치