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CDC2510C

새 설계에 권장하지 않음

PC SDRAM 레지스터 DIMM을 지원하는 3.3V PLL 클록 드라이버 설계 지원 문서 개정판 1.2

지금 주문
데이터 시트
CDC2510C은(는) 새 설계에 권장하지 않습니다.
이 제품은 기존 고객을 위해 계속 제공됩니다. 새로운 설계는 대체 제품을 고려해야 합니다.
open-in-new 대안 비교
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
CDCVF2510 활성 DRAM 애플리케이션용 10개 출력을 지원하는 3.3V 위상 동기 루프 클록 드라이버 Can achieve better performance

CDC2510C

새 설계에 권장하지 않음
데이터 시트 지금 주문

제품 상세 정보

Function Zero-delay Output frequency (max) (MHz) 125 Number of outputs 10 Core supply voltage (V) 3.3 Output skew (ps) 250 Operating temperature range (°C) to Rating Catalog
Function Zero-delay Output frequency (max) (MHz) 125 Number of outputs 10 Core supply voltage (V) 3.3 Output skew (ps) 250 Operating temperature range (°C) to Rating Catalog
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • Use CDCVF2510A as a Replacement for this Device
  • Designed to Meet PC SDRAM Registered DIMM Design Support Document Rev. 1.2
  • Spread Spectrum Clock Compatible
  • Operating Frequency 25 MHz to 125 MHz
  • Static tPhase Error Distribution at 66 MHz to 100 MHz is ±150 ps
  • Drop-In Replacement for TI CDC2510A With Enhanced Performance
  • Jitter (cyc - cyc) at 66 MHz to 100 MHz is |100 ps|
  • Available in Plastic 24-Pin TSSOP
  • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
  • Distributes One Clock Input to One Bank of Ten Outputs
  • External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
  • On-Chip Series Damping Resistors
  • No External RC Network Required
  • Operates at 3.3 V
  • Use CDCVF2510A as a Replacement for this Device
  • Designed to Meet PC SDRAM Registered DIMM Design Support Document Rev. 1.2
  • Spread Spectrum Clock Compatible
  • Operating Frequency 25 MHz to 125 MHz
  • Static tPhase Error Distribution at 66 MHz to 100 MHz is ±150 ps
  • Drop-In Replacement for TI CDC2510A With Enhanced Performance
  • Jitter (cyc - cyc) at 66 MHz to 100 MHz is |100 ps|
  • Available in Plastic 24-Pin TSSOP
  • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
  • Distributes One Clock Input to One Bank of Ten Outputs
  • External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
  • On-Chip Series Damping Resistors
  • No External RC Network Required
  • Operates at 3.3 V

The CDC2510C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2510C operates at VCC = 3.3 V . It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC2510C does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2510C requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.

The CDC2510C is characterized for operation from 0°C to 85°C.

For application information refer to application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC) (literature number SCAA039).

The CDC2510C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2510C operates at VCC = 3.3 V . It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC2510C does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2510C requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.

The CDC2510C is characterized for operation from 0°C to 85°C.

For application information refer to application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC) (literature number SCAA039).
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* Data sheet CDC2510C: 3.3-V Phase-Lock Loop Clock Driver datasheet (Rev. A) 2004/12/02

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치