CDCL1810A

Name: CDCL1810A
Brand: TI
SKU: CDCL1810A
Price: 5.933 USD

활성

개별 출력 활성화/비활성화를 지원하는 1.8V 1~10 고성능 차동 클록 버퍼

지금 주문

데이터 시트

document-pdfAcrobat CDCL1810A 1.8V, 10 Output, High-Performance Clock Distributor datasheet (영어) PDF | HTML

CDCL1810A

활성

데이터 시트

지금 주문

제품 상세 정보

Function

Clock buffer, Clock divider

Additive RMS jitter (typ) (fs)

Output frequency (max) (MHz)

650

Number of outputs

Output supply voltage (V)

1.8

Core supply voltage (V)

1.8

Output skew (ps)

Features

I2C interface

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

CML

Input type

LVDS

Function

Clock buffer, Clock divider

Additive RMS jitter (typ) (fs)

Output frequency (max) (MHz)

650

Number of outputs

Output supply voltage (V)

1.8

Core supply voltage (V)

1.8

Output skew (ps)

Features

I2C interface

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

CML

Input type

LVDS

VQFN (RGZ)

49 mm² 7 x 7

othersSingle 1.8 V Supply
High-Performance Clock Distributor with 10 Outputs
Low Input-to-Output Additive Jitter: as low as 10fs RMS
Low-Voltage Differential Signaling (LVDS) Input, 100Ω
Differential On-Chip Termination, up to 650 MHz Frequency
Differential Current Mode Logic (CML) Outputs, 50Ω
Single-Ended On-Chip Termination, up to 650 MHz Frequency
Two Groups of Five Outputs Each with Independent Frequency
Division Ratios
Output Frequency Derived with Divide Ratios of 1, 2, 4, 5,
8, 10, 16, 20, 32, 40, and 80
Meets ANSI TIA/EIA-644-A-2001 LVDS Standard Requirements
Power Consumption: 410 mW Typical
Output Enable Control for Each Output
SDA/SCL Device Management Interface
48-pin VQFN (RGZ) Package
Industrial Temperature Range: –40°C to +85°C

othersSingle 1.8 V Supply
High-Performance Clock Distributor with 10 Outputs
Low Input-to-Output Additive Jitter: as low as 10fs RMS
Low-Voltage Differential Signaling (LVDS) Input, 100Ω
Differential On-Chip Termination, up to 650 MHz Frequency
Differential Current Mode Logic (CML) Outputs, 50Ω
Single-Ended On-Chip Termination, up to 650 MHz Frequency
Two Groups of Five Outputs Each with Independent Frequency
Division Ratios
Output Frequency Derived with Divide Ratios of 1, 2, 4, 5,
8, 10, 16, 20, 32, 40, and 80
Meets ANSI TIA/EIA-644-A-2001 LVDS Standard Requirements
Power Consumption: 410 mW Typical
Output Enable Control for Each Output
SDA/SCL Device Management Interface
48-pin VQFN (RGZ) Package
Industrial Temperature Range: –40°C to +85°C

The CDCL1810A is a high-performance clock distributor. The programmable dividers, P0 and P1, give a high flexibility to the ratio of the output frequency to the input frequency: F_OUT = F_IN/P, where P (P0,P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80.

The CDCL1810A supports one differential LVDS clock input and a total of 10 differential CML outputs. The CML outputs are compatible with LVDS receivers if they are ac-coupled.

With careful observation of the input voltage swing and common-mode voltage limits, the CDCL1810A can support a single-ended clock input as outlined in Pin Configuration and Functions.

All device settings are programmable through the SDA/SCL, serial two-wire interface. The serial interface is 1.8V tolerant only.

The device operates in a 1.8V supply environment and is characterized for operation from –40°C to +85°C. The CDCL1810A is available in a 48-pin QFN (RGZ) package.

The CDCL1810A supports one differential LVDS clock input and a total of 10 differential CML outputs. The CML outputs are compatible with LVDS receivers if they are ac-coupled.

With careful observation of the input voltage swing and common-mode voltage limits, the CDCL1810A can support a single-ended clock input as outlined in Pin Configuration and Functions.

All device settings are programmable through the SDA/SCL, serial two-wire interface. The serial interface is 1.8V tolerant only.

The device operates in a 1.8V supply environment and is characterized for operation from –40°C to +85°C. The CDCL1810A is available in a 48-pin QFN (RGZ) package.

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기타 클록 버퍼 찾기

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관심 가지실만한 유사 제품

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CDCL1810

활성

1.8V 1~10 고성능 차동 클록 버퍼 P2P to CDCL1810A with divider syncronisation and output group phase adjustment

기술 자료

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1개 모두 보기

	유형	직함		날짜
*	Data sheet	CDCL1810A 1.8V, 10 Output, High-Performance Clock Distributor datasheet	PDF \| HTML	2014/11/05

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

시뮬레이션 모델

CDCL1810A IBIS Software

SNAC065.ZIP (23 KB) - IBIS Model

다운로드

설계 툴

CLOCK-TREE-ARCHITECT — 클록 트리 아키텍트 프로그래밍 소프트웨어

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.

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시뮬레이션 툴

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TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)

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