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Function Real-time clock Iq (typ) (mA) 0.26 Features 10-MHz external clock frequency, 12/24 hour, Parallel bus interface Rating Catalog Operating temperature range (°C) -40 to 85 Supply voltage (max) (V) 5.5 Supply voltage (min) (V) 4.5
Function Real-time clock Iq (typ) (mA) 0.26 Features 10-MHz external clock frequency, 12/24 hour, Parallel bus interface Rating Catalog Operating temperature range (°C) -40 to 85 Supply voltage (max) (V) 5.5 Supply voltage (min) (V) 4.5
PLCC (FN) 28 155.0025 mm² 12.45 x 12.45
  • Full function real time clock/calendar
    • 12/24 hour mode timekeeping
    • Day of week and day of years counters
    • Four selectable oscillator frequencies
    • Parallel Resonant Oscillator
  • Two 16-bit timers
    • 10 MHz external clock frequency
    • Programmable multi-function output
    • Flexible re-trigger facilities
  • Power fail features
    • Internal power supply switch to external battery
    • Power Supply Bus glitch protection
    • Automatic log of time into RAM at power failure
  • On-chip interrupt structure
    • Periodic, alarm, timer and power fail interrupts
  • Up to 44 bytes of CMOS RAM
  • INTR/MFO/T1 pins programmable High/Low and push-pull or open drain

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

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Copyright © 1995 National Semiconductor Corporation
Learn About and Influence The Site

  • Full function real time clock/calendar
    • 12/24 hour mode timekeeping
    • Day of week and day of years counters
    • Four selectable oscillator frequencies
    • Parallel Resonant Oscillator
  • Two 16-bit timers
    • 10 MHz external clock frequency
    • Programmable multi-function output
    • Flexible re-trigger facilities
  • Power fail features
    • Internal power supply switch to external battery
    • Power Supply Bus glitch protection
    • Automatic log of time into RAM at power failure
  • On-chip interrupt structure
    • Periodic, alarm, timer and power fail interrupts
  • Up to 44 bytes of CMOS RAM
  • INTR/MFO/T1 pins programmable High/Low and push-pull or open drain

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

(size: 390486)
WebDIRECT™ Search

WebDIRECT™ is a trademark of Coris, Inc.,
a wholly-owned subsidiary of R.R. Donnelley & Sons Company.

How to download and view our Data Sheets
Our Data Sheets and other documents are available for downloading in the Portable Document Format (PDF). You can view and print these documents using the Adobe Acrobat Reader. If you do not already have Adobe Acrobat Reader installed and configured on your system, then click here.

Copyright © 1995 National Semiconductor Corporation
Learn About and Influence The Site

The DP8570A is intended for use in microprocessor based systems where information is required for multi-tasking, data logging or general time of day/date information. This device is implemented in low voltage silicon gate microCMOS technology to provide low standby power in battery back-up environments. The circuit's architecture is such that it looks like a contiguous block of memory or I/O ports. The address space is organized as 2 software selectable pages of 32 bytes. This includes the Control Registers, the Clock Counters, the Alarm Compare RAM, the Timers and their data RAM, and the Time Save RAM. Any of the RAM locations that are not being used for their intended purpose may be used as general purpose CMOS RAM.

Time and date are maintained from 1/100 of a second to year and leap year in a BCD format, 12 or 24 hour modes. Day of week, day of month and day of year counters are provided. Time is controlled by an on-chip crystal oscillator requiring only the addition of the crystal and two capacitors. The choice of crystal frequency is program selectable.

Two independent multifunction 10 MHz 16-bit timers are provided. These timers operate in four modes. Each has its own prescaler and can select any of 8 possible clock inputs. Thus, by programming the input clocks and the timer counter values a very wide range of timing durations can be achieved. The range is from about 400 ns (4.915 MHz oscillator) to 65,535 seconds (18 hrs., 12 min.).

Power failure logic and control functions have been integrated on chip. This logic is used by the TCP to issue a power fail

interrupt, and lock out the µp interface. The time power fails may be logged into RAM automatically when VBB > VCC. Additionally, two supply pins are provided. When VBB > VCC, internal circuitry will automatically switch from the main supply to the battery supply. Status bits are provided to indicate initial application of battery power, system power, and low battery detect.


The DP8570A is intended for use in microprocessor based systems where information is required for multi-tasking, data logging or general time of day/date information. This device is implemented in low voltage silicon gate microCMOS technology to provide low standby power in battery back-up environments. The circuit's architecture is such that it looks like a contiguous block of memory or I/O ports. The address space is organized as 2 software selectable pages of 32 bytes. This includes the Control Registers, the Clock Counters, the Alarm Compare RAM, the Timers and their data RAM, and the Time Save RAM. Any of the RAM locations that are not being used for their intended purpose may be used as general purpose CMOS RAM.

Time and date are maintained from 1/100 of a second to year and leap year in a BCD format, 12 or 24 hour modes. Day of week, day of month and day of year counters are provided. Time is controlled by an on-chip crystal oscillator requiring only the addition of the crystal and two capacitors. The choice of crystal frequency is program selectable.

Two independent multifunction 10 MHz 16-bit timers are provided. These timers operate in four modes. Each has its own prescaler and can select any of 8 possible clock inputs. Thus, by programming the input clocks and the timer counter values a very wide range of timing durations can be achieved. The range is from about 400 ns (4.915 MHz oscillator) to 65,535 seconds (18 hrs., 12 min.).

Power failure logic and control functions have been integrated on chip. This logic is used by the TCP to issue a power fail

interrupt, and lock out the µp interface. The time power fails may be logged into RAM automatically when VBB > VCC. Additionally, two supply pins are provided. When VBB > VCC, internal circuitry will automatically switch from the main supply to the battery supply. Status bits are provided to indicate initial application of battery power, system power, and low battery detect.


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* Data sheet DP8570A Timer Clock Peripheral (TCP) datasheet 2004/05/03

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TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
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PLCC (FN) 28 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
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  • 조립 위치

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